UPSTREAM: vboot: Select SoC-specific configuration for all Chrome OS boards
Some Chrome OS boards previously didn't have a hardcoded vboot
configuration (e.g. STARTS_IN_BOOTBLOCK/_ROMSTAGE, SEPARATE_VERSTAGE,
etc.) selected from their SoC and mainboard Kconfig files, and instead
relied on the Chrome OS build system to pass in those options
separately. Since there is usually only one "best" vboot configuration
for a certain board and there is often board or SoC code specifically
written with that configuration in mind (e.g. memlayout), these options
should not be adjustable in menuconfig and instead always get selected
by board and SoC Makefiles (as opposed to some external build system).
(Removing MAINBOARD_HAS_CHROMEOS from Urara because vboot support for
Pistachio/MIPS was never finished. Trying to enable even post-romstage
vboot leads to weird compiler errors that I don't want to track down
now. Let's stop pretending this board has working Chrome OS support
because it never did.)
Change-Id: Ie50b79b1bb1acd10ed64332eaa763f0a6cb9ea17
Original-Change-Id: Ibddf413568630f2e5d6e286b9eca6378d7170104
Original-Reviewed-on: https://review.coreboot.org/19022
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id: 1210b41283
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/462007
This commit is contained in:
parent
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12 changed files with 34 additions and 1 deletions
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@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_512
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select BOOTBLOCK_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select SPI_FLASH_WINBOND
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select CPU_IMGTEC_PISTACHIO
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select COMMON_CBFS_SPI_WRAPPER
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@ -25,6 +25,9 @@ config NORTHBRIDGE_INTEL_HASWELL
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if NORTHBRIDGE_INTEL_HASWELL
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config VBOOT
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select VBOOT_STARTS_IN_ROMSTAGE
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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default "northbridge/intel/haswell/bootblock.c"
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@ -32,6 +32,9 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE
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if NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE
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config VBOOT
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select VBOOT_STARTS_IN_ROMSTAGE
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config USE_NATIVE_RAMINIT
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bool "Use native raminit"
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default y
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@ -29,6 +29,7 @@ config SOC_BROADCOM_CYGNUS
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if SOC_BROADCOM_CYGNUS
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config CHROMEOS
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select VBOOT_STARTS_IN_BOOTBLOCK
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select SEPARATE_VERSTAGE
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select RETURN_FROM_VERSTAGE
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@ -39,6 +39,9 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_INTEL_FIRMWARE
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select HAVE_SPI_CONSOLE_SUPPORT
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config VBOOT
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select VBOOT_STARTS_IN_ROMSTAGE
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config BOOTBLOCK_CPU_INIT
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string
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default "soc/intel/baytrail/bootblock/bootblock.c"
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@ -46,6 +46,9 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_INTEL_FIRMWARE
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select HAVE_SPI_CONSOLE_SUPPORT
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config VBOOT
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select VBOOT_STARTS_IN_ROMSTAGE
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config BOOTBLOCK_CPU_INIT
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string
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default "soc/intel/braswell/bootblock/bootblock.c"
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@ -46,6 +46,9 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_SPI_CONSOLE_SUPPORT
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select CPU_INTEL_COMMON
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config VBOOT
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select VBOOT_STARTS_IN_ROMSTAGE
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config BOOTBLOCK_CPU_INIT
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string
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default "soc/intel/broadwell/bootblock/cpu.c"
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@ -18,6 +18,8 @@ config SOC_NVIDIA_TEGRA210
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if SOC_NVIDIA_TEGRA210
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config CHROMEOS
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select VBOOT_STARTS_IN_BOOTBLOCK
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select SEPARATE_VERSTAGE
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select VBOOT_OPROM_MATTERS
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config MAINBOARD_DO_DSI_INIT
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@ -13,6 +13,7 @@ config SOC_QC_IPQ40XX
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if SOC_QC_IPQ40XX
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config CHROMEOS
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select VBOOT_STARTS_IN_BOOTBLOCK
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select RETURN_FROM_VERSTAGE
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select SEPARATE_VERSTAGE
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select VBOOT_VBNV_FLASH
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@ -12,6 +12,7 @@ config SOC_QC_IPQ806X
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if SOC_QC_IPQ806X
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config CHROMEOS
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select VBOOT_STARTS_IN_BOOTBLOCK
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select VBOOT_VBNV_FLASH
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select SEPARATE_VERSTAGE
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select RETURN_FROM_VERSTAGE
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@ -10,3 +10,10 @@ config CPU_SAMSUNG_EXYNOS5250
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select HAVE_HARD_RESET
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bool
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default n
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if CPU_SAMSUNG_EXYNOS5250
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config VBOOT
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select VBOOT_STARTS_IN_ROMSTAGE
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endif
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@ -9,3 +9,10 @@ config CPU_SAMSUNG_EXYNOS5420
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select RELOCATABLE_MODULES
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bool
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default n
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if CPU_SAMSUNG_EXYNOS5420
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config VBOOT
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select VBOOT_STARTS_IN_ROMSTAGE
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endif
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