Shawn Nematbakhsh ae51ac971e auron: Convert mainboard to use soc/intel/broadwell ... Switch from the haswell cpu/northbridge/southbridge interface to the soc/intel/broadwell interface. - Use new headers where appropriate - Remove code that is now done by the SOC generic code - Update GPIO map to drop LP specific handling - Update INT15 handlers, drop all but the boot display hook Auron port of Samus commit 715dbb06e9. BUG=chrome-os-partner:31286 TEST=Compile only. BRANCH=None. Change-Id: Ie8a660dd139c382929485ff458b5945e8ad72d23 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/213957 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>		2014-08-27 04:02:18 +00:00
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arch	Linux copy of mips/ashldi3.c	2014-08-26 21:02:17 +00:00
console	vboot2: implement select_firmware for pre-romstage verification	2014-06-30 18:45:09 +00:00
cpu	haswell: Update microcode revision	2014-07-29 04:37:18 +00:00
device	i2c: Add software_i2c driver for I2C debugging and emulation	2014-05-19 20:34:31 +00:00
drivers	spi: Support Macronix MX25U6435F SPI ROM.	2014-08-07 22:45:49 +00:00
ec	chromeec: provide proto v3 over i2c support	2014-08-07 22:38:07 +00:00
include	smbios: add funtion for smbios type17	2014-08-12 02:40:38 +00:00
lib	fix how to interpret board id read from gpios	2014-08-09 07:05:56 +00:00
mainboard	auron: Convert mainboard to use soc/intel/broadwell	2014-08-27 04:02:18 +00:00
northbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
soc	broadwell: Read and save HSIO version from ME in romstage	2014-08-27 04:02:10 +00:00
southbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
superio	pnp: Allow setting of misc register 0xf4 in device tree	2013-12-20 00:37:38 +00:00
vendorcode	vboot: Introduce kconfig variable for VBNV backing storage	2014-08-25 04:52:51 +00:00
Kconfig	Enable publishing of board ID where supported	2014-07-30 23:41:23 +00:00