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Kein Yuan bc01a3df80 Baytrail: changes to USB3 PLL VCO and iCLK PLL current on BYT-M/D CPU 
Intel will be making slight changes to USB3 PLL VCO and iCLK PLL current
on C0 stepping of BYT-M/D C0 stepping in order to meet the high demands
for these processors.

Pre-conversion materials are compatible with USB PLL VCO current increase.
Post-conversion materials ARE REQUIRED to be run with increased USB3 PLL
VCO current.

BUG=chrome-os-partner:31199
TEST=Boot Rambi, then read USHPHY_CDN_PLL_CONTROL and verify register
has new value.

Change-Id: Ie9c3d0afd54ea7ced2c76ebb948de95be0828fa0
Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/211337
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit df20eca47ca0ff33baf5d554ef11dd2b35706a5d)
Reviewed-on: https://chromium-review.googlesource.com/205970
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217772
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Kenji Chen <kenji.chen@intel.com>
Tested-by: Kenji Chen <kenji.chen@intel.com>
2014-09-12 00:56:25 +00:00
..
arch arm64: Replace CONFIG_* variables with {read/write}_current 2014-09-11 20:00:10 +00:00
console console: Allow bootblock console on MIPS 2014-09-01 11:06:29 +00:00
cpu imgtec/danube: Add support for ImgTec Danube SoC 2014-09-01 11:06:39 +00:00
device i2c: Add software_i2c driver for I2C debugging and emulation 2014-05-19 20:34:31 +00:00
drivers Add support for GigaDevice GD25LQ64C/GD25LB64C SPI ROM. 2014-08-28 01:16:15 +00:00
ec chromeec: Clear post code before reboot to RO 2014-09-02 20:25:38 +00:00
include arm, arm64, x86: add vprintk to early console 2014-08-30 09:15:26 +00:00
lib cbfs: change 1 message level to WARNING if cbfs can't find specific data 2014-09-11 20:00:41 +00:00
mainboard veyron_pinky: Add board ID support 2014-09-12 00:56:20 +00:00
northbridge coreboot: Rename coreboot_ram stage to ramstage 2014-05-07 23:30:23 +00:00
soc Baytrail: changes to USB3 PLL VCO and iCLK PLL current on BYT-M/D CPU 2014-09-12 00:56:25 +00:00
southbridge coreboot: Rename coreboot_ram stage to ramstage 2014-05-07 23:30:23 +00:00
superio
vendorcode coreboot: rk3288: update romstage & mainboard 2014-09-04 15:46:53 +00:00
Kconfig arch/mips: Add base MIPS architecture support 2014-09-01 11:05:57 +00:00