Jincheng Li ad05c65d72 soc/intel/xeon_sp: Initialize SPI before using it ... fast_spi_cache_bios_region() refers to the SPI BAR before it is initialized. Therefore, move the initialization before this function to obtain the correct value. If SPI is not initialized before use, an incorrect MTRR item is observed: [DEBUG] 0x00000000fffff005: PHYBASE2: Address = 0x00000000fffff000, WP [DEBUG] 0x000ffffffffff800: PHYMASK2: Length = 0x0000000000001000, Valid TESTED=Build and boot on intel/avenuecity CRB, with below log: [DEBUG] 0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP [DEBUG] 0x000fffffff000800: PHYMASK2: Length = 0x0000000001000000, Valid Change-Id: I8a755d2d18a567c09c5a66b03d4fdda5ba603133 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88046 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>		2025-06-13 15:23:23 +00:00
..
amd	soc/amd/glinda: Don't let OS put debug UART into D3	2025-06-04 18:00:06 +00:00
cavium
example/min86
ibm/power9
intel	soc/intel/xeon_sp: Initialize SPI before using it	2025-06-13 15:23:23 +00:00
mediatek	soc/mediatek: Don't attempt de-assert PERST# without pci_root_bus	2025-06-12 01:27:01 +00:00
nvidia
qualcomm	soc/qualcomm/x1p42100: Enable basic PCIe support	2025-05-30 04:21:29 +00:00
rockchip
samsung
sifive
ti
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx	soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup	2025-01-23 00:41:01 +00:00