Disable Enhanced Intel SpeedStep Technology (EIST) to prevent
OS-controlled P-state transitions. This improves consistent CPU
frequency bevahior across all cores, which is critical for real-time
applictaions requiring deterministic performance.
The existing devicetree parameter 'eist_enable' only configures the
IA32_MISC_ENABLE register but does not affect the FSP-S parameter
'Eist'. This results in FSP re-enabling EIST during silicon
initialization, overriding the register setting.
Override the FSP-S 'Eist' parameter at mainboard level rather than
fixing it in SoC code, since devicetree parameters default to 0 when
unset and would disable EIST on boards that rely on FSP defaults.
Change-Id: Ic83246d88607a8ed0c9815e306934bcf0bf8f016
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88965
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
a1b7f5e1b8