Align DDR and IMEM address definitions with memory layout specifications. Modify CBMEM top address accordingly. Changes include: - Declaring new memory regions in symbols_common.h. - Defining base addresses and sizes for these regions in memlayout.ld. - Marking these regions as reserved in soc_read_resources() to prevent overwrites by coreboot. - Modifying CBMEM top address. TEST=Create an image.serial.bin and ensure it boots on X1P42100. Change-Id: I77c95198d6e42635ab7ecaac41fbd29133cb0fa0 Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89348 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> |
||
|---|---|---|
| .. | ||
| amd | ||
| cavium | ||
| example/min86 | ||
| ibm/power9 | ||
| intel | ||
| mediatek | ||
| nvidia | ||
| qualcomm | ||
| rockchip | ||
| samsung | ||
| sifive | ||
| ti | ||
| ucb/riscv | ||
| xilinx | ||