Swathi Tamilselvan fba92daed3 soc/qualcomm/x1p42100: Clean up DDR and IMEM memory layout ... Align DDR and IMEM address definitions with memory layout specifications. Modify CBMEM top address accordingly. Changes include: - Declaring new memory regions in symbols_common.h. - Defining base addresses and sizes for these regions in memlayout.ld. - Marking these regions as reserved in soc_read_resources() to prevent overwrites by coreboot. - Modifying CBMEM top address. TEST=Create an image.serial.bin and ensure it boots on X1P42100. Change-Id: I77c95198d6e42635ab7ecaac41fbd29133cb0fa0 Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89348 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>		2025-10-06 08:04:58 +00:00
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amd	acpi: Move most of HEST ACPI table to common code	2025-09-30 23:52:09 +00:00
cavium
example/min86
ibm/power9	soc/power9/rom_media.c: find CBFS in PNOR	2025-08-28 20:14:01 +00:00
intel	soc/intel/pantherlake: Use CPU ID mask for all stepping	2025-10-01 21:08:08 +00:00
mediatek	soc/mediatek/mt8196: Add DVFS support for the second SoC SKU	2025-10-04 02:47:43 +00:00
nvidia
qualcomm	soc/qualcomm/x1p42100: Clean up DDR and IMEM memory layout	2025-10-06 08:04:58 +00:00
rockchip
samsung
sifive
ti
ucb/riscv
xilinx