coreboot/src/soc
Shawn Nematbakhsh 27fae3e670 baytrail: DPTF: Enable mainboard-specific PPCC
Allow PL1 to be set at the mainboard level.

BUG=chrome-os-partner:26436
TEST=Run DPTF utility, verify specified PL1 settings are still in place.
Modify PL1 settings at mainboard level, verify that changes are
reflected in DPTF utility.
BRANCH=Rambi.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id05701385867420e4d0f129f38dda0d3580abaff
Reviewed-on: https://chromium-review.googlesource.com/189576
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2014-03-12 01:27:18 +00:00
..
intel baytrail: DPTF: Enable mainboard-specific PPCC 2014-03-12 01:27:18 +00:00
nvidia tegra124: Add a macro specifically for configuring the I2C controller clocks. 2014-03-08 02:24:35 +00:00
samsung arm: Redesign, clarify and clean up cache related code 2014-01-29 21:33:35 +00:00
Kconfig ARM: Generalize armv7 as arm. 2013-10-02 09:18:44 +00:00
Makefile.inc armv7: Move Exynos from 'cpu' to 'soc'. 2013-10-01 08:16:46 +00:00