The CPUCP (CPU Control Processor) binary is currently stored
uncompressed in the RO region. To save space in the RO section
while maintaining fast boot performance in normal mode, split the
CPUCP CBFS entry into two distinct files:
1. cpucp_rw: Stored in FW_MAIN_A and FW_MAIN_B with no compression
for performance.
2. cpucp_ro: Stored in the COREBOOT (RO) region with LZMA
compression to save flash space.
Update the loading logic in cpucp_load_reset.c to select the
appropriate binary based on the current vboot mode (Normal vs.
Recovery).
BUG=None
TEST=Verified that CPUCP loads from 'cpucp_rw' during normal boot
and 'cpucp_ro' when vboot recovery is triggered.
Normal Mode:
```
[INFO ] CBFS: Found 'fallback/cpucp_rw' @0xc8640 size 0x79244
in mcache @0x8669d628
```
Recovery Mode:
```
[INFO ] CBFS: Found 'fallback/cpucp_ro' @0xc8640 size 0x79244
in mcache @0x8669d628
```
Change-Id: Iec5294beec4377b13f8b7354d86055d5907c6556
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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| amd | ||
| cavium | ||
| example/min86 | ||
| ibm/power9 | ||
| intel | ||
| mediatek | ||
| nvidia | ||
| qualcomm | ||
| rockchip | ||
| samsung | ||
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| ti | ||
| ucb/riscv | ||
| xilinx | ||