c731fd720c
Without explicit DDR5 support, print_spd_info() was decoding DDR5 DIMMs with the DDR4 SPD layout, so banks, ranks, rows, columns, and module size were all displaying incorrect values. Add DDR5-specific decoding in spd_bin.c using JESD400-5 byte positions. Define these offsets in ddr5.h and branch in each getter when dram_type is DDR5 so printed SPD info matches the actual module. Fix printk reporting DIMM module size to only report "per channel" when the DIMM actually contains multiple channels. TEST=build/boot on out-of-tree board Erying SRMJ4 and Starlabs Starbook MTL. Verify DIMM info printed in cbmem console is correct. Change-Id: I7f418db3f89c67c2a71b2c327bb511a78faf7300 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91145 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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| .. | ||
| azalia_codec | ||
| dram | ||
| azalia_device.h | ||
| cardbus.h | ||
| device.h | ||
| fw_cfg.h | ||
| fw_cfg_if.h | ||
| gpio.h | ||
| i2c.h | ||
| i2c_bus.h | ||
| i2c_simple.h | ||
| mdio.h | ||
| mmio.h | ||
| path.h | ||
| pci.h | ||
| pci_def.h | ||
| pci_ehci.h | ||
| pci_ids.h | ||
| pci_mmio_cfg.h | ||
| pci_ops.h | ||
| pci_rom.h | ||
| pci_type.h | ||
| pciexp.h | ||
| pcix.h | ||
| pnp.h | ||
| pnp_def.h | ||
| pnp_ops.h | ||
| pnp_type.h | ||
| resource.h | ||
| smbus.h | ||
| smbus_def.h | ||
| smbus_host.h | ||
| soundwire.h | ||
| spi.h | ||
| usbc_mux.h | ||
| xhci.h | ||