Julius Werner 7466ffc035 rk3288: Fix some PLL divisors and improve clock code ... This patch does some general cleanup in the Rockchip clock code, and adds some more assertions regarding the PLL VCO and output frequency ranges. It changes all PLL divisors to use the lowest values that can still hit the target frequency, since higher NR values lead to higher jitter and higher NO values increase power draw. Also change DDR3 frequency code to hardcode the optimal divisors for certail frequencies. As a little hack we will interpret 666000000 to actually mean 666666666.6P (and analogous for 533MHz), since that's what you usually want for memory. BUG=chrome-os-partner:32139 TEST=Boot on veyron_pinky rev2, check that dpll_is shown as 666666666 in /sys/kernel/debug/clk/clk_summary. Change-Id: I4f3c39641955a95c6dfbe9334035eb670b138bf0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/221801		2014-10-14 23:59:06 +00:00
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imgtec	New mechanism to define SRAM/memory map with automatic bounds checking	2014-10-03 09:09:36 +00:00
intel	broadwell: me: Fix typo and add missing phase state	2014-10-10 11:39:33 +00:00
marvell	cosmos: add template for soc and board files	2014-10-09 20:44:46 +00:00
nvidia	tegra132: remove framebuffer reservation	2014-10-09 16:42:21 +00:00
qualcomm	New mechanism to define SRAM/memory map with automatic bounds checking	2014-10-03 09:09:36 +00:00
rockchip	rk3288: Fix some PLL divisors and improve clock code	2014-10-14 23:59:06 +00:00
samsung	New mechanism to define SRAM/memory map with automatic bounds checking	2014-10-03 09:09:36 +00:00
Kconfig	cosmos: add template for soc and board files	2014-10-09 20:44:46 +00:00
Makefile.inc	cosmos: add template for soc and board files	2014-10-09 20:44:46 +00:00