Docs: Use markdown autolinks instead of Sphinx doc directive

Several files use embedded reStructuredText blocks in order to use the
:doc: directive to reference other markdown files using a relative path.
MyST Parser supports a similar feature using the standard Markdown
autolink (angled bracket) syntax, so use this instead as it is cleaner.
Both methods use the first heading of the linked file as the text shown
in the reference, though MyST Parser also supports the standard [link
text](../path/to/file.md) syntax to explicitly set the link text.

Note that when using the autolink syntax, `project:` must be prepended
to the relative path as it expects a URI scheme for all autolinks. This
is not required when using the separate text and URI syntax.

Before:
    ```{eval-rst}
    Example text :doc:`../relative/path`.
    ```

After:
    Example text <project:../relative/path.md>

Using the Markdown syntax also avoids formatting issues if any plain
text in the eval-rst block uses Markdown formatting syntax where they
would unintentionally be parsed differently due to text being parsed as
reStructuredText.

Some :doc: instances still remain as they are used within reST style
tables in an eval-rst block, so these were left as is since the Markdown
syntax would be invalid in that context.

[1]: https://myst-parser.readthedocs.io/en/latest/syntax/cross-referencing.html#autolinks

Change-Id: I8828bf7efe13de6d6f628f6b64151fbd25289fa5
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>

Documentation/getting_started/build_system.md

@@ -75,9 +75,7 @@ $(call add_intermediate, add_mrc_data)
 
 Note that the second line must start with a tab, not spaces.
 
-```{eval-rst}
-See also :doc:`../tutorial/managing_local_additions`.
-```
+See also <project:../tutorial/managing_local_additions.md>.
 
 #### FMAP region support
 With the addition of FMAP flash partitioning support to coreboot, there was a

Documentation/mainboard/acer/g43t-am3.md

@@ -122,10 +122,8 @@ $ sudo flashrom \
   -w coreboot.rom
 ```
 
-```{eval-rst}
 In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
+<project:../../tutorial/flashing_firmware/index.md>.
 
 ### External flashing
 

Documentation/mainboard/asrock/h77pro4-m.md

@@ -115,10 +115,8 @@ $ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
 The use of `--noverify-all` is required since the Management Engine
 region is not readable even by the host.
 
-```{eval-rst}
 In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
+<project:../../tutorial/flashing_firmware/index.md>.
 
 ## Hardware monitoring and fan control
 

Documentation/mainboard/asrock/h81m-hds.md

@@ -4,9 +4,7 @@ This page describes how to run coreboot on the [ASRock H81M-HDS].
 
 ## Required proprietary blobs
 
-```{eval-rst}
-Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
-```
+Please see <project:../../northbridge/intel/haswell/mrc.bin.md>.
 
 ## Building coreboot
 
@@ -75,9 +73,8 @@ facing towards the bottom of the board.
   in coreboot. The `coretemp` driver can still be used for accurate CPU
   temperature readings from an OS.
 
-```{eval-rst}
-Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
-```
+Please also see
+<project:../../northbridge/intel/haswell/known-issues.md>.
 
 ## Untested
 

Documentation/mainboard/gigabyte/ga-g41m-es2l.md

@@ -30,9 +30,7 @@ This motherboard [also works with Libreboot](https://libreboot.org/docs/install/
 
 ## Preparation
 
-```{eval-rst}
-For more datails how to get sources and build the toolchain, see :doc:`../../tutorial/part1`.
-```
+For more datails how to get sources and build the toolchain, see <project:../../tutorial/part1.md>.
 
 ### Devuan 4 Chimaera
 
@@ -140,10 +138,8 @@ Built gigabyte/ga-g41m-es2l (GA-G41M-ES2L)
 
 ## Flashing coreboot
 
-```{eval-rst}
 In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
+<project:../../tutorial/flashing_firmware/index.md>.
 
 ### Do backup
 

Documentation/mainboard/hp/compaq_8300_usdt.md

@@ -59,7 +59,8 @@ Wake on LAN is active works great.
 ### SuperIO
 
 This board has a Nuvoton NPCD379 SuperIO chip. Fan speed and PS/2 keyboard work
-fine using coreboot's existing code for :doc:`../../superio/nuvoton/npcd378`.
+fine using coreboot's existing code for
+<project:../../superio/nuvoton/npcd378.md>.
 
 [Compaq Elite 8300 USDT]: https://support.hp.com/gb-en/product/hp-compaq-elite-8300-ultra-slim-pc/5232866
 [HP]: https://www.hp.com/

Documentation/mainboard/intel/dq67sw.md

@@ -104,11 +104,9 @@ the PCI configuration space of the LPC Interface Bridge, is set.
 It is possible to program the chip is to attach an external programmer
 with an SOIC-8 clip.
 
-```{eval-rst}
 Another way is to boot the vendor firmware in UEFI mode and exploit the
 unpatched S3 Boot Script vulnerability. See this page for a similar procedure:
-:doc:`../lenovo/ivb_internal_flashing`.
-```
+<project:../lenovo/ivb_internal_flashing.md>.
 
 On this specific board it is possible to prevent the BLE bit from being set
 when it resumes from S3. One entry in the S3 Boot Script must be modified,
@@ -126,12 +124,10 @@ The boot script contains an entry that writes 0x02 to memory at address
 Interface Bridge [0][1]. The value 0x02 sets the BLE bit, and the modification
 prevents this by making it write a 0 instead.
 
-```{eval-rst}
 After suspending and resuming the board, the BIOS region can be flashed with
 a coreboot image, e.g. using flashrom. Note that the ME region is not readable,
 so the `--noverify-all` flag is necessary. Please refer to the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
+<project:../../tutorial/flashing_firmware/index.md>.
 
 ## Hardware monitoring and fan control
 

Documentation/mainboard/lenovo/Ivy_Bridge_series.md

@@ -37,9 +37,7 @@ This information is valid for all supported models, except T430s, [T431s](t431s.
   exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB.
 * ROM chip size should be set to 12MiB.
 
-```{eval-rst}
-Please also have a look at :doc:`../../tutorial/flashing_firmware/index`.
-```
+Please also have a look at <project:../../tutorial/flashing_firmware/index.md>.
 
 ## Splitting the coreboot.rom
 

Documentation/mainboard/supermicro/x10slm-f.md

@@ -4,16 +4,12 @@ This section details how to run coreboot on the [Supermicro X10SLM+-F].
 
 ## Required proprietary blobs
 
-```{eval-rst}
-Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
-```
+Please see <project:../../northbridge/intel/haswell/mrc.bin.md>.
 
 ## Building coreboot
 
-```{eval-rst}
 If you haven't already, build the coreboot toolchain as described in
-:doc:`../../tutorial/part1`.
-```
+<project:../../tutorial/part1.md>.
 
 A fully working image should be possible so long as you have the
 Haswell `mrc.bin` file. You can set the basic config with the following
@@ -40,10 +36,8 @@ Now, run `make` to build the coreboot image.
 
 ## Flashing coreboot
 
-```{eval-rst}
 In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
+<project:../../tutorial/flashing_firmware/index.md>.
 
 ### Internal programming
 
@@ -119,11 +113,8 @@ eventually start. There is no such delay when running coreboot.
 
 ## ECC DRAM
 
-```{eval-rst}
 ECC DRAM seems to work, but please see
-:doc:`../../northbridge/intel/haswell/mrc.bin`
-for caveats.
-```
+<project:../../northbridge/intel/haswell/mrc.bin.md> for caveats.
 
 ## Known issues
 
@@ -139,9 +130,8 @@ for caveats.
   in coreboot. The `coretemp` driver can still be used for accurate CPU
   temperature readings from an OS, and hence the OS can do fan control.
 
-```{eval-rst}
-Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
-```
+Please also see
+<project:../../northbridge/intel/haswell/known-issues.md>.
 
 ## Untested
 

Documentation/northbridge/intel/haswell/known-issues.md

@@ -5,11 +5,9 @@ mainboard, there might be additional issues to those listed here.
 
 ## PCIe graphics
 
-```{eval-rst}
 Using a PCIe graphics card for display output is not currently
-supported. This is because :doc:`./mrc.bin` requires workarounds to
+supported. This is because <project:mrc.bin.md> requires workarounds to
 have such a feature working correctly.
-```
 
 However, there is a [patch on Gerrit][hsw-gfx-gerrit] that allows PCIe
 graphics to be used for display output. This patch is not guaranteed to