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coreboot/src
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Aaron Durbin 2903a3eec6 baytrail: add C0 microcode update 
Include C0 microcode drop.

BUG=None
BRANCH=rambi,squawks
TEST=Built. Booted B3 part.

Change-Id: If454658235cd5a7b8640de0b3fa12dccddb0e9f6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182080
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
2014-01-10 01:50:00 +00:00
..
arch Add initial aarch64 support 2013-12-19 02:33:34 +00:00
console ARM: Generalize armv7 as arm. 2013-10-02 09:18:44 +00:00
cpu armv8: add support for armv8 cpu 2014-01-07 02:48:47 +00:00
device pnp: Allow setting of misc register 0xf4 in device tree 2013-12-20 00:37:38 +00:00
drivers Haswell/falco/peppy/slippy: continue to clean up FUI. 2013-12-19 01:17:37 +00:00
ec chromeec: add function to reboot on unexpected image 2014-01-10 00:11:54 +00:00
include baytrail: snapshot power state in romstage 2014-01-09 20:15:55 +00:00
lib baytrail: snapshot power state in romstage 2014-01-09 20:15:55 +00:00
mainboard rambi: dptf: Set critical thresholds 2014-01-10 00:11:50 +00:00
northbridge peppy and falco: set panel power timings in northbridge, using devicetree, not mainboards 2013-12-23 08:55:32 +00:00
soc baytrail: add C0 microcode update 2014-01-10 01:50:00 +00:00
southbridge lynxpoint: Don't enable SMI handling of TCO 2013-12-18 21:25:27 +00:00
superio pnp: Allow setting of misc register 0xf4 in device tree 2013-12-20 00:37:38 +00:00
vendorcode chromeos: add VBOOT_REFCODE_INDEX option 2013-12-17 21:27:07 +00:00
Kconfig armv8: add support for armv8 cpu 2014-01-07 02:48:47 +00:00