Bora Guvendik 15b903e1fd soc/intel/pantherlake: Add DDR5 memory type debug message ... This commit introduces a debug message to the DDR5 memory type initialization process within the Panther Lake SoC. By adding this log, developers can gain better insights when diagnosing issues related to DDR5 memory configurations. BUG=none TEST=Verify the debug message is displayed during DDR5 initialization. Change-Id: I77ceea0f7a29983dd2e4ad1af26a0383721d7ca0 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89331 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>		2025-09-26 19:04:01 +00:00
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amd	soc/amd/common/block/psp: Add comments	2025-09-25 16:06:54 +00:00
cavium	soc/cavium: Fix non matching types	2024-08-30 07:34:47 +00:00
example/min86
ibm/power9	soc/power9/rom_media.c: find CBFS in PNOR	2025-08-28 20:14:01 +00:00
intel	soc/intel/pantherlake: Add DDR5 memory type debug message	2025-09-26 19:04:01 +00:00
mediatek	soc/mediatek/mt8196: Set RTC EOSC calibration to 8 seconds	2025-09-26 02:24:29 +00:00
nvidia	arch/arm: Add a few ARM targets as supported by CLANG	2024-08-23 10:40:01 +00:00
qualcomm	soc/qualcomm/qclib: Improve logging on invalid MRC cache data	2025-09-24 03:25:06 +00:00
rockchip	arch/arm: Add a few ARM targets as supported by CLANG	2024-08-23 10:40:01 +00:00
samsung	samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'	2025-01-15 08:32:16 +00:00
sifive	tree: Remove unused <assert.h>	2024-11-19 00:40:04 +00:00
ti
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx	soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup	2025-01-23 00:41:01 +00:00