coreboot/src/soc/amd
Maximilian Brune 1158e26a26 soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.

In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.

Change-Id: Ie34bb2abc0211963b2613d1b50b1767df31c1062
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2025-04-11 20:05:07 +00:00
..
cezanne soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default 2025-04-11 20:05:07 +00:00
common src/soc/amd/* : Move CPU init in common code 2025-04-11 15:41:44 +00:00
genoa_poc src/soc/amd/* : Move CPU init in common code 2025-04-11 15:41:44 +00:00
glinda src/soc/amd/* : Move CPU init in common code 2025-04-11 15:41:44 +00:00
mendocino src/soc/amd/* : Move CPU init in common code 2025-04-11 15:41:44 +00:00
phoenix src/soc/amd/* : Move CPU init in common code 2025-04-11 15:41:44 +00:00
picasso src/soc/amd/* : Move CPU init in common code 2025-04-11 15:41:44 +00:00
stoneyridge tree: Remove unused <assert.h> 2024-11-19 00:40:04 +00:00