Duncan Laurie 1050e7d3be broadwell: Add romstage usbdebug support ... This function will enable the EHCI port 1 on haswell/broadwell PCH to act as USB debug port. This is hardcoded to port 1. The EHCI controller must be kept enabled if CONFIG_USBDEBUG is enabled so this logic is added to the ehci ramstage driver. BUG=chrome-os-partner:28234 TEST=enable CONFIG_USBDEBUG and build+boot with USB debug output. Note that libpayload does not support usbdebug yet (I have separate patches for that) so no payload output is visible. Change-Id: I704a4786438173b2f3ee2c246636f5a24d8b428c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/199412 Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2014-05-15 05:11:48 +00:00
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arch	coreboot: Introduce stage-specific architecture for coreboot	2014-05-09 04:41:47 +00:00
console	Add stage information to coreboot banner	2014-05-14 20:49:21 +00:00
cpu	coreboot: Introduce stage-specific architecture for coreboot	2014-05-09 04:41:47 +00:00
device	coreboot: Introduce stage-specific architecture for coreboot	2014-05-09 04:41:47 +00:00
drivers	SPI: Add Eon EN25S64 support.	2014-05-09 22:00:56 +00:00
ec	chromeos: Unconditionally clear the EC recovery request	2014-05-07 03:33:49 +00:00
include	cbmem: use a single id to name mapping table	2014-05-14 22:53:16 +00:00
lib	cbmem: use a single id to name mapping table	2014-05-14 22:53:16 +00:00
mainboard	storm: initialize dynamic cbmem properly	2014-05-14 20:52:37 +00:00
northbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
soc	broadwell: Add romstage usbdebug support	2014-05-15 05:11:48 +00:00
southbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
superio	pnp: Allow setting of misc register 0xf4 in device tree	2013-12-20 00:37:38 +00:00
vendorcode	vboot: Add a new post code for TPM failure	2014-05-12 22:12:41 +00:00
Kconfig	coreboot: Introduce stage-specific architecture for coreboot	2014-05-09 04:41:47 +00:00