Aaron Durbin 0eddbf7648 vboot: fix vboot_load_ramstage() ... During a refactor the stage->load address was being returned as an entry point. That is only true when the first instruction is the entry point of the stage. Fix the handling of the load and entry points. BUG=chrome-os-partner:30784 BRANCH=None TEST=Building still works. vboot still runs on rush. Change-Id: I65a93c1c785569190406cd23006ea840c0011936 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/211010 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org>		2014-08-05 02:39:09 +00:00
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arch	arm: add _end symbol to bootblock.ld	2014-08-04 16:34:12 +00:00
console	vboot2: implement select_firmware for pre-romstage verification	2014-06-30 18:45:09 +00:00
cpu	haswell: Update microcode revision	2014-07-29 04:37:18 +00:00
device	i2c: Add software_i2c driver for I2C debugging and emulation	2014-05-19 20:34:31 +00:00
drivers	vboot2: read secdata and nvdata	2014-07-23 02:29:18 +00:00
ec	vboot2: read dev and recovery switch	2014-07-02 00:45:22 +00:00
include	Publish the board ID value in coreboot table, when configured	2014-07-30 23:41:05 +00:00
lib	Include board ID calculations only when necessary	2014-07-30 23:41:10 +00:00
mainboard	ryu: remove unused files	2014-08-05 02:38:51 +00:00
northbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
soc	tegra: correct gpio_index_to_port() calculation	2014-08-05 02:39:04 +00:00
southbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
superio	pnp: Allow setting of misc register 0xf4 in device tree	2013-12-20 00:37:38 +00:00
vendorcode	vboot: fix vboot_load_ramstage()	2014-08-05 02:39:09 +00:00
Kconfig	Enable publishing of board ID where supported	2014-07-30 23:41:23 +00:00