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Publish the board ID value in coreboot table, when configured

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Board ID value is usually of interest to bootloaders. Instead of
duplicating the board ID discovery code in different bootloaders let's
determine it in coreboot and publish it through coreboot table, when
configured.

BUG=chrome-os-partner:30489
TEST=none yet

Change-Id: Iee247c44a1c91dbcedcc9058e8742c75ff951f43
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210116
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
Vadim Bendebury 2014-07-28 16:03:07 -07:00 • committed by chrome-internal-fetch
commit b2057a02db
4 changed files with 37 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

8
src/Kconfig
View file

@ -996,6 +996,14 @@ config DEBUG_COVERAGE
If enabled, the code coverage hooks in coreboot will output some
information about the coverage data that is dumped.
config BOARD_ID_SUPPORT
bool "Discover board ID and store it in coreboot table"
default n
help
If enabled, coreboot discovers the board id of the hardware it is
running on and reports it through the coreboot table to the rest of
the system.
config TERTIARY_BOARD_ID
bool "Interpret board ID GPIOs as tertiary inputs"
default n if ARCH_X86

8
src/include/boot/coreboot_tables.h
View file

@ -244,6 +244,14 @@ struct lb_x86_rom_mtrr {
uint32_t index;
};
#define LB_TAG_BOARD_ID 0x0025
struct lb_board_id {
uint32_t tag;
uint32_t size;
/* Board ID as retrieved from the board revision GPIOs. */
uint32_t board_id;
};
/* The following structures are for the cmos definitions table */
#define LB_TAG_CMOS_OPTION_TABLE 200
/* cmos header record */

2
src/lib/Makefile.inc
View file

@ -58,7 +58,6 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c
romstage-y += compute_ip_checksum.c
romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += gcc.c
romstage-$(CONFIG_TERTIARY_BOARD_ID) += tristate_gpios.c
ramstage-y += hardwaremain.c
ramstage-y += selfboot.c
@ -90,6 +89,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += edid.c
ramstage-y += memrange.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
ramstage--${CONFIG_TERTIARY_BOARD_ID} += tristate_gpios.c
# The CBMEM implementations are chosen based on CONFIG_DYNAMIC_CBMEM.
ifeq ($(CONFIG_DYNAMIC_CBMEM),y)

24
src/lib/coreboot_table.c
View file

@ -25,6 +25,7 @@
#include <boot/coreboot_tables.h>
#include <string.h>
#include <version.h>
#include <boardid.h>
#include <device/device.h>
#include <stdlib.h>
#include <cbfs.h>
@ -217,9 +218,9 @@ static void lb_vbnv(struct lb_header *header)
#endif
}
#if CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE
static void lb_vboot_handoff(struct lb_header *header)
{
#if CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE
void *addr;
uint32_t size;
struct lb_range *vbho;
@ -232,12 +233,23 @@ static void lb_vboot_handoff(struct lb_header *header)
vbho->size = sizeof(*vbho);
vbho->range_start = (intptr_t)addr;
vbho->range_size = size;
}
#else
static inline void lb_vboot_handoff(struct lb_header *header) {}
#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
}
#endif /* CONFIG_CHROMEOS */
static void lb_board_id(struct lb_header *header)
{
#if CONFIG_BOARD_ID_SUPPORT
struct lb_board_id *bid;
bid = (struct lb_board_id *)lb_new_record(header);
bid->tag = LB_TAG_BOARD_ID;
bid->size = sizeof(*bid);
bid->board_id = board_id();
#endif
}
static void lb_x86_rom_cache(struct lb_header *header)
{
#if CONFIG_ARCH_X86
@ -574,6 +586,10 @@ unsigned long write_coreboot_table(
/* pass along the vboot_handoff address. */
lb_vboot_handoff(head);
#endif
/* Add board ID if available */
lb_board_id(head);
add_cbmem_pointers(head);
/* Add board-specific table entries, if any. */