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Kane Chen 0da45307be auron: Move SPD related files/information to spd directory 
Auron port of Samus commit f40e447cee

BUG=chrome-os-partner:31286
TEST=compile ok and make sure the spd index is right on auron
     boot to OS
BRANCH=None

Change-Id: Idf8f58dc48ff7dd2481177aa377628cfa032b699
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/214820
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
2014-08-29 03:11:51 +00:00
..
arch arm64: provide API for coordinating secondary CPU bringup 2014-08-29 03:10:47 +00:00
console vboot2: implement select_firmware for pre-romstage verification 2014-06-30 18:45:09 +00:00
cpu haswell: Update microcode revision 2014-07-29 04:37:18 +00:00
device i2c: Add software_i2c driver for I2C debugging and emulation 2014-05-19 20:34:31 +00:00
drivers Add support for GigaDevice GD25LQ64C/GD25LB64C SPI ROM. 2014-08-28 01:16:15 +00:00
ec chromeec: Add ACPI device for PD MCU and handle related EC host event 2014-08-29 02:57:00 +00:00
include smbios: add funtion for smbios type17 2014-08-12 02:40:38 +00:00
lib rmodule: Fix rmodule.ld for 64-bit 2014-08-28 01:14:24 +00:00
mainboard auron: Move SPD related files/information to spd directory 2014-08-29 03:11:51 +00:00
northbridge coreboot: Rename coreboot_ram stage to ramstage 2014-05-07 23:30:23 +00:00
soc tegra132: add option to bring up and init secondary cpu 2014-08-29 03:11:47 +00:00
southbridge coreboot: Rename coreboot_ram stage to ramstage 2014-05-07 23:30:23 +00:00
superio pnp: Allow setting of misc register 0xf4 in device tree 2013-12-20 00:37:38 +00:00
vendorcode vboot: Introduce kconfig variable for VBNV backing storage 2014-08-25 04:52:51 +00:00
Kconfig Enable publishing of board ID where supported 2014-07-30 23:41:23 +00:00