This commit addresses the GPIO configuration for DDR5 on Intel's
PTLRVP mainboard. Specifically, it extends support for the DDR5
configuration by adding a case for PTLP_DDR5_RVP in the GPIO
differential table function. This modification ensures proper handling
of GPIO settings when DDR5 memory is configured, thereby improving
system stability and compatibility.
BUG=none
TEST=Boot with DDR5 configuration.
Change-Id: I3745c0a25e84a0f41dced44613cfd638c12fb1d3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87872
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
394dfcaa7b