mb/*/*/early_init.c: Remove unused included southbridge

Change-Id: Ia3fda208f5cb2e0d8a1e4da2c4392bc0f326d1ed
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84076
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes Haouas 2024-08-24 09:47:57 +02:00 committed by Felix Singer
commit 5ee650727b
32 changed files with 0 additions and 33 deletions

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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <bootblock_common.h>
#include <southbridge/intel/i82801jx/i82801jx.h>
#include <northbridge/intel/x4x/x4x.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8720f/it8720f.h>

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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <bootblock_common.h>
#include <southbridge/intel/i82801jx/i82801jx.h>
#include <northbridge/intel/x4x/x4x.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8720f/it8720f.h>

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@ -2,7 +2,6 @@
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/nct6776/nct6776.h>
#include <superio/nuvoton/common/nuvoton.h>

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@ -5,7 +5,6 @@
#include <device/pci_ops.h>
#include <device/pnp_ops.h>
#include <option.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>

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@ -2,7 +2,6 @@
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>

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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <bootblock_common.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>

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@ -2,7 +2,6 @@
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>

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@ -2,7 +2,6 @@
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>

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@ -2,7 +2,6 @@
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>

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@ -2,7 +2,6 @@
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>

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@ -2,7 +2,6 @@
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>

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@ -2,7 +2,6 @@
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>

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@ -4,7 +4,6 @@
#include <device/pnp_ops.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/pei_data.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>

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@ -2,7 +2,6 @@
#include <bootblock_common.h>
#include <device/pnp_type.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>

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@ -2,8 +2,6 @@
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>

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@ -2,7 +2,6 @@
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>

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@ -4,7 +4,6 @@
#include <stdint.h>
#include <arch/io.h>
#include <superio/smsc/sio1007/sio1007.h>
#include <southbridge/intel/bd82x6x/pch.h>
#define SIO_PORT 0x164e

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@ -3,7 +3,6 @@
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/smsc/sch5545/sch5545.h>
#include <superio/smsc/sch5545/sch5545_emi.h>

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@ -3,7 +3,6 @@
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8772f/it8772f.h>

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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <bootblock_common.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <northbridge/intel/pineview/pineview.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8721f/it8721f.h>

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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h>

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@ -4,7 +4,6 @@
#include <console/console.h>
#include <device/pnp_ops.h>
#include <northbridge/intel/pineview/pineview.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8720f/it8720f.h>

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@ -2,7 +2,6 @@
#include <bootblock_common.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h>

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@ -4,7 +4,6 @@
#include <superio/nuvoton/npcd378/npcd378.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <device/pci_ops.h>
#include <southbridge/intel/bd82x6x/pch.h>
void bootblock_mainboard_early_init(void)
{

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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <bootblock_common.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/smsc/lpc47n217/lpc47n217.h>
#include <ec/hp/kbc1126/ec.h>

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@ -5,7 +5,6 @@
#include <arch/io.h>
#include <superio/smsc/sio1007/sio1007.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <southbridge/intel/bd82x6x/pch.h>
#define SIO_PORT 0x164e

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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pci_ops.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
#include <northbridge/intel/sandybridge/sandybridge.h>

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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pci_ops.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
#include <northbridge/intel/sandybridge/sandybridge.h>

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@ -2,7 +2,6 @@
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <ec/lenovo/pmh7/pmh7.h>
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
#include <northbridge/intel/sandybridge/sandybridge.h>

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@ -2,7 +2,6 @@
#include <stdint.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <southbridge/intel/bd82x6x/pch.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
{

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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/sandybridge/raminit.h>
#include <southbridge/intel/bd82x6x/pch.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
{

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@ -6,7 +6,6 @@
#include <device/pnp_ops.h>
#include <device/pnp.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/ite/it8783ef/it8783ef.h>
#include <superio/ite/common/ite.h>