coreboot/src/soc
Gabe Black a2df8f3a9c Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus.
These functions are intended to start and end a transaction on the bus and so
need to manage the CS line.

BUG=None
TEST=Used a Logic16 to watch the SPI bus as coreboot attempted to use it to
talk to the EC. With this change, CS was set (low) during the transaction when
before it wasn't.
BRANCH=None

Change-Id: I37992dc2e51dec878d565ebea1da586bdcac6400
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173953
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
2013-10-23 05:21:11 +00:00
..
intel baytrail: SMM support 2013-10-23 04:08:23 +00:00
nvidia Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus. 2013-10-23 05:21:11 +00:00
samsung exynos: Fix the name of the chip_operations structures. 2013-10-10 00:32:06 +00:00
Kconfig ARM: Generalize armv7 as arm. 2013-10-02 09:18:44 +00:00
Makefile.inc armv7: Move Exynos from 'cpu' to 'soc'. 2013-10-01 08:16:46 +00:00