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Duncan Laurie 0c3c3be3fc haswell: Report x32 memory as "x8 or x32" 
There is only one bit for memory width reporting, either x16 or
other.  With x32 memory this code is reporting it as x8 so instead
report "x8 or x32" in this condition.

BUG=chrome-os-partner:23449
BRANCH=samus
TEST=emerge-samus chromeos-coreboot-samus

Change-Id: I2a7c49bcb8de19084947b9dc42b93140641886fc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174120
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2013-10-23 21:27:19 +00:00
..
arch armv4: add a stub for dcache_line_bytes() 2013-10-23 05:21:27 +00:00
console ARM: Generalize armv7 as arm. 2013-10-02 09:18:44 +00:00
cpu x86: Add SMM helper functions to MP infrastructure 2013-10-23 04:08:19 +00:00
device ARM: Generalize armv7 as arm. 2013-10-02 09:18:44 +00:00
drivers drivers/gma: remove unused code 2013-10-11 20:36:54 +00:00
ec chromeec: Implement full battery workaround at 6% 2013-09-16 23:31:17 +00:00
include x86: Add SMM helper functions to MP infrastructure 2013-10-23 04:08:19 +00:00
lib coreboot: config to cache ramstage outside CBMEM 2013-10-11 23:27:01 +00:00
mainboard samus: Disable SMBUS controller 2013-10-23 21:27:16 +00:00
northbridge haswell: Report x32 memory as "x8 or x32" 2013-10-23 21:27:19 +00:00
soc Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus. 2013-10-23 05:21:11 +00:00
southbridge lynxpoint: Allow to always route USB3 ports to XHCI 2013-10-22 21:42:00 +00:00
superio Drop prototype guarding for romcc 2013-05-10 11:55:20 -07:00
vendorcode beltino: Fix recovery button 2013-10-22 00:00:24 +00:00
Kconfig coreboot: config to cache ramstage outside CBMEM 2013-10-11 23:27:01 +00:00