erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

lynxpoint: Allow to always route USB3 ports to XHCI

Browse source 
This will make USB keyboards connected to USB3 ports work
in libpayload on Beltino.

BUG=chrome-os-partner:23396
BRANCH=none
TEST=Use USB keyboard on Beltino in dev mode screen

Change-Id: I70b03d733bd9e4c8be5673b48bd2196effa8a5e7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173640
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
This commit is contained in:
Stefan Reinauer 2013-10-17 17:00:26 -07:00 • committed by chrome-internal-fetch
commit c691a69d30
3 changed files with 13 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

3
src/mainboard/google/beltino/devicetree.cb
View file

@ -68,6 +68,9 @@ chip northbridge/intel/haswell
# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
register "icc_clock_disable" = "0x01220000"
# Route all USB ports to XHCI per default
register "xhci_default" = "1"
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
device pci 15.0 on end # Serial I/O DMA

3
src/southbridge/intel/lynxpoint/chip.h
View file

@ -104,6 +104,9 @@ struct southbridge_intel_lynxpoint_config {
* [24] = CLKOUT_ITPXDP
*/
uint32_t icc_clock_disable;
/* Route USB ports to XHCI per default */
uint8_t xhci_default;
};
extern struct chip_operations southbridge_intel_lynxpoint_ops;

8
src/southbridge/intel/lynxpoint/usb_xhci.c
View file

@ -26,6 +26,8 @@
#include <arch/io.h>
#include "pch.h"
typedef struct southbridge_intel_lynxpoint_config config_t;
static u32 usb_xhci_mem_base(device_t dev)
{
u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@ -294,6 +296,7 @@ static void usb_xhci_init(device_t dev)
u32 reg32;
u16 reg16;
u32 mem_base = usb_xhci_mem_base(dev);
config_t *config = dev->chip_info;
/* D20:F0:74h[1:0] = 00b (set D0 state) */
reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
@ -357,8 +360,11 @@ static void usb_xhci_init(device_t dev)
/* Reset ports that are disabled or
* polling before returning to the OS. */
usb_xhci_reset_usb3(dev, 0);
}
} else
#endif
/* Route all ports to XHCI */
if (config->xhci_default)
outb(0xca, 0xb2);
}
static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,