Existing SAR infrastructure supports only revision 0 of the SAR tables.
This patch modifies it to extend support for intel wifi 6 and wifi 6e
configurations as per the connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
The SAR table and WGDS configuration block sizes were static in the
legacy SAR file format. Following is the format of the new binary file.
+------------------------------------------------------------+
| Field | Size | Description |
+------------------------------------------------------------+
| Marker | 4 bytes | "$SAR" |
+------------------------------------------------------------+
| Version | 1 byte | Current version = 1 |
+------------------------------------------------------------+
| SAR table | 2 bytes | Offset of SAR table from start of |
| offset | | the header |
+------------------------------------------------------------+
| WGDS | 2 bytes | Offset of WGDS table from start of |
| offset | | the header |
+------------------------------------------------------------+
| Data | n bytes | Data for the different tables |
+------------------------------------------------------------+
This change supports both the legacy and the new format of SAR file
BUG=b:193665559
TEST=Checked the SSDT entries for WRDS, EWRD and WGDS with different
binaries generated by setting different versions in the config.star
Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
IDS (Integrated Debug Services) options are meant to be enabled when one
wants to debug AGESA. Since they are compile-time options, using Kconfig
is the logical choice. Currently, none of the options builds.
Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and Asus A88XM-E does not change.
Change-Id: I465627c19c9856e58ca94aa0efedbddb6baaf3f6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
The `ASSERT` macro is already defined in `src/include/assert.h`, and
AGESA's definition is never used. On Asus A88XM-E, toggling the value of
the `IDSOPT_ASSERT_ENABLED` macro does not change the resulting binary
when using reproducible builds. Attempting to use AGESA's definition of
the `ASSERT` macro results in build errors:
In file included from src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c:56:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c: In function 'GetType4Type7Info':
src/vendorcode/amd/agesa/f15tn/Include/Ids.h:371:33: error: statement with no effect [-Werror=unused-value]
#define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE));
Given that coreboot's definition of `ASSERT` is more useful, drop
AGESA's broken definition and the useless `IDSOPT_ASSERT_ENABLED` macro.
Also remove the `IdsAssert` function, as it is no longer used anywhere.
Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical.
Change-Id: Ia4e5dbfd3d2e5cec979b8b16fbc11d1ca8a0661e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Disable reading of vdram/vddq/vmddr to reduce access of I2C
to reduce DRAM init time by about 30ms.
The values were only needed by HQA report and not needed on
production units.
BUG=b:195274787
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I32cd68fb8b52cec6e145d6772475fde0130ca6ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56850
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Support the config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT to limit DRAM
frequency counts to reduce DRAM initialization time by about 100ms.
BUG=b:195274787
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Ibcb9a50c24f428358ef682b64946d4c91ebd81d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Sync the MemInfoHob.h with current FSP code.
BUG=b:190339677
TEST=dmidecode -t 17 can show the memory information.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I80d1252b1f12b164d4f6d3a01221507cdfbe4d08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This symbol is only used in generating a default fmap.
Change-Id: I8d92eba9978cdad5795b0f5755e1d75db7b3cb2d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Enable the impedance tracking for channel 2 and channel 3.
The impedance tracking can compensate the settings of impedance
when the temperature changes.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I047ab70bb59736a8ba8ae75ab15659900c784342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56620
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable RSA and SHA for cezanne since support has been added to the PSP.
Also picasso and cezanne have different enums definitions for
hash algorithm, so split that out into chipset.c.
BUG=b:187906425
TEST=boot guybrush, check cbmem -t and the logs
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I725b0cac801ac0429f362a83aa58a8b9de158550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The headers added are generated as per FSP v2237_00.
Previous FSP version was v2207_01.
Changes Include:
- Add VccInAuxImonIccImax in FspsUpd.h
- Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h
BUG=b:192199787
BRANCH=None
TEST=Build and boot brya
Change-Id: Ie291204a3fa0b9451c418c84bd40a17ef08a436c
Cq-Depend:chrome-internal:3970327,chrome-internal:3925290
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55896
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the implementation for vcore voltage control.
Also remove the reporting of vio18 because it is fixed during DRAM init,
and we won't provide drivers for reading or writing it.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56106
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CONFIG(CHROMEOS) in DRAM calibration code was incorrectly used to
identify implementations for Chromebooks (in coreboot) so we want to
introduce a new flag FOR_COREBOOT to prevent confusion.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic7a6e24f41c1fda167b5d6bb2d8a2c5c79dda8de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56158
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FirmwareVersionInfoHob.h is removed in JSL FSP v2376 so
remove it from Jasper Lake vendorcode.
BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patch in relation chain
and verify the version output prints no junk data observed.
couple of lines from logs are as below.
Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1
Change-Id: Iad0429630665f50dbc1541487c9061dd1a19907c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45908
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update MdePkg/Include/IndustryStandard/SmBios.h to avoid compilation
errors through safeguarding definitions with DISPLAY_FSP_VERSION_INFO_2
Kconfig.
BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patches in relation chain
and verify the version output prints no junk data observed.
Couple of lines from logs are as below.
Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1
Change-Id: I9698861be1f969ddca7f171767a54ac486502c74
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45906
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To support DRAM HQA HV/LV test, add an interface for adjusting the DRAM
voltage in DRAM fast calibration flow.
Normal boot flow will not be affected.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I4dbb4cb546e6e60693743ffe26b0df28ea501618
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55752
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This UPD to enable/disable the non-graphics HD audio controller was
added in FSP build version 1.0.3.1, so sync the header file in coreboot
with this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I15eee45dc5d12a420eb688eaa5879c92b6d1b2c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
After ChromeOS NVS was moved to a separate allocation and the use
of multiple OperationRegions, maintaining the fixed offsets is not
necessary.
Use actual structure size for OperationRegions, but align the
allocations to 8 bytes or sizeof(uint64_t).
Change-Id: I9c73b7c44d234af42c571b23187b924ca2c3894a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable generation of DMI Type 17 data on Cezanne.
BUG=b:184124605
TEST="dmidecode --type 17" in OS on Majolica
Change-Id: Iaa89ee1ce6efa0280f17a443e07571a1190873a6
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Sync the MemInfoHob.h with current FSP code.
BUG=b:190339677
TEST=dmidecode -t 17 can show the memory information.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifd3e6a264131437c67d17ec80f37f5e8d0a03a79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
EDK2 mandates HOB to be in increments of qword (8). This HOB has 13
elements which causes it be padded with 4 bytes of garbage. This
results in coreboot failing intermittently with invalid data. Add
"number of entries" field to specify the number of valid entries in
the table.
BUG=b:190153208
Cq-depend: chrome-internal:3889619
TEST=verify HOB is present and correct size (13) is reported
Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55237
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The new cezanne PSP release added support for these svcs. So add those
functionality back to cezanne psp_verstage.
BUG=b:187906425
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Update FSP headers for Tiger Lake platform generated based on FSP
version 4133 to include post PRQ UPDs.
BUG=b:188452018
BRANCH=none
TEST=build voxel
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54811
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The AMD FSP is using a new structure for USB and USB C phy settings.
This patch removes old, unused structures, adds the new one and
enables the devicetree interface for it.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
The FSP-M/S/T related headers added are generated as per FSP v3162.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ie6e6db704bcf86034fc9a3423101f0391ba2327e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54869
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit ce0e2a0140 (drivers/intel/fsp2_0:
use FSP to allocate APEI BERT memory region) adds a mechanism to reserve
the BERT region inside the coreboot code, so we can get rid of the
workaround to reserve it in the FSP and return the location in a HOB.
mcfg->bert_size defaults to 0 which makes the FSP not generate the
corresponding HOB, but that field is planned to be removed at least on
Cezanne, so don't explicitly set it to 0.
BUG=b:169934025
TEST=BERT table that gets generated in a follow-up patch for Picasso
points to expected BERT region and Linux is able to access, decode and
display it.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaca89b47793bf9982181560f026459a18e7db134
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52584
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The headers added are generated as per FSP v2162_00.
Previous FSP version was v2117_00.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Remove DisableDimmMc*Ch* Upds in FspmUpd.h
- Add DisableMc*Ch* Upds in FspmUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h
Change DisableDimmMc*Ch* to DisableMc*Ch* in meminit.c to avoid
compilation failure other change related to UPDs name change will be
part of next patch in relation chain.
BUG=b:187189546
BRANCH=None
TEST=Build and boot ADLRVP using all the patch in relation chain.
Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e
Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913
Cq-Depend: chromium:TODO
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54083
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is the DRAM initialization code from the reference
implementation released by Mediatek for MT8195.
The DRAM calibration code can be taken as a standalone
library, used by different boot loaders for initializing
DRAM and following a different coding style (coreboot was
using Linux Kernel coding style), so we have to put it
in vendor code folder.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com>
Change-Id: Iada3ec5ae8a39a8e9253caba550c834d486dddcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
gcc 11 suspects missing braces here, but it seems the line should be
executed in all cases, so unindent it.
Change-Id: I7b8cacd48e86284c5145c4e8ffb6add75a743108
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
gcc 11.1 complains when we're passing a type* into a function that was
declared to get a type[], even if the ABI has identical parameter
passing for both.
To prepare for newer compilers, adapt to this added constraint.
Change-Id: I5a1b3824a85a178431177620c4c0d5fddc993b4f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This is some leftover omitted during 00660F01 removal, since
corresponding CPU and northbridge code is not present in the tree
already.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib7ccbc088766b5a4f59c47bd48790c6a2af8ca61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This HOB describes the PCI routing table. It will be consumed by
coreboot to generate the _PRT ACPI object.
BUG=b:184766519, b:184766197
TEST=Build guybrush
Cq-Depend: chrome-internal:3794981
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib790004b88dfaf7671534f657c7735f6718114db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
