Kangheui Won ce0fad5e39 soc/amd/cezanne: enable crypto in psp_verstage ... Enable RSA and SHA for cezanne since support has been added to the PSP. Also picasso and cezanne have different enums definitions for hash algorithm, so split that out into chipset.c. BUG=b:187906425 TEST=boot guybrush, check cbmem -t and the logs Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I725b0cac801ac0429f362a83aa58a8b9de158550 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2021-07-21 16:53:17 +00:00
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amd	soc/amd/cezanne: enable crypto in psp_verstage	2021-07-21 16:53:17 +00:00
cavium	src: use ARRAY_SIZE where possible	2021-02-15 11:30:40 +00:00
eltan	vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT	2021-04-06 07:01:31 +00:00
google	timestamp,vc/google/chromeos/cr50: Add timestamp for enable update	2021-07-05 10:50:06 +00:00
intel	vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00	2021-07-13 15:14:56 +00:00
mediatek	vc/mediatek/mt8195: Remove redundant code	2021-07-13 01:46:30 +00:00
siemens	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
Makefile.inc	soc/mediatek/mt8192: initialize DRAM using vendor reference code	2021-03-08 03:15:43 +00:00