Eric Lai 66b090a226 vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSP ... Sync the MemInfoHob.h with current FSP code. BUG=b:190339677 TEST=dmidecode -t 17 can show the memory information. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifd3e6a264131437c67d17ec80f37f5e8d0a03a79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-06-10 05:36:59 +00:00
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amd	soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB	2021-06-07 16:04:36 +00:00
cavium	src: use ARRAY_SIZE where possible	2021-02-15 11:30:40 +00:00
eltan	vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT	2021-04-06 07:01:31 +00:00
google	mb/google: Move ECFW_RW setting for non-ChromeEC boards	2021-04-30 06:48:56 +00:00
intel	vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSP	2021-06-10 05:36:59 +00:00
mediatek	vendor/mediatek: Add MT8195 dram initialization code	2021-05-14 04:00:38 +00:00
siemens	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
Makefile.inc	soc/mediatek/mt8192: initialize DRAM using vendor reference code	2021-03-08 03:15:43 +00:00