We need to figure out if we should just grow stage0. My inclination is
to say 'yes'.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@877 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@871 f3766cd6-281f-0410-b1cd-43a5c92072e9
Far fewer warnings than before :-)
TODO: Document the DIMM_SETTINGS variable.
FIx up fidvid code.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@869 f3766cd6-281f-0410-b1cd-43a5c92072e9
some prints, and fixes a null pointer deref bug that has been in the
k8 code since the dawn of time.
We get here:
CPU 804 Mhz
Etherboot 5.4.3 (GPL) http://etherboot.org
Drivers: VIA-VELOCITY/PCI Images: ELF
Protocols: DHCP TFTP
Relocating _text from: [000100e0,000349c0) to [0007b720,000a0000)
Boot from (N)etwork or (Q)uit?
Probing pci nic...
Probing isa nic...
<sleep>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@867 f3766cd6-281f-0410-b1cd-43a5c92072e9
multiple links. The way this was done in v2 was a big confusing; this way is
less so.
The changes are easy. Getting them right has been hard :-)
First, for a k8 north that has three links, you can name each one as follows:
pci0@18,0
pci1@18,0
pci2@18,0
We have to have the same pcidevfn on these because that is how the k8 works.
But the unit numbers (pci0, pci1, etc.) distinguish them.
The dts will properly generate a "v3 device code"
compatible static tree that puts the links in the right place in the
data structure.
The changes to dts are trivial.
As before, dts nodes with children are understood to be a bridge.
But what if there is a dts entry like this:
pci1@18,0 {/config/("northbridge/amd/k8/pci");};
This entry has no children in the dts.
How does dt compiler know it is a bridge? It can not know unless
we add information to the dts for that northbridge part.
To ensure that all bridge devices are detected, we support the following:
if a dts node for a device has a bridge property, e.g.:
{
device_operations = "k8_ops";
bridge;
};
The dt compiler will treat it as a bridge whether it has children or not.
Why would a device not have children? Because it might be attached to a
pci or other socket, and we don't know at build time if the socket is empty,
or what might be in the socket.
This code has been tested on dbe62 and k8 simnow, and works on each.
It is minimal in size and it does what we need. I hope it resolves our
discussion for now. We might want to improve or change the device code
later but, at this point, forward motion is important -- I'm on a deadline for
a very important demo Oct. 22!
Also included in this patch are new debug prints in k8 north.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@865 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@862 f3766cd6-281f-0410-b1cd-43a5c92072e9
size indicated by byte 31 of SPD.
Memory is still not working; hanging in dqs training.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@854 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@851 f3766cd6-281f-0410-b1cd-43a5c92072e9
This code has been tested on dbe62, and builds for qemu as well.
the next step is testing on simnow.
k8.h: add more prototypes and some required inline functions.
cpu.h: same
serengeti: expand defines in mainboard.h, though we need a better
mechanism; continue to fix initram.c, add new support files to Makefile
lib/console.c: include globalvars.h
lib/lar.c: Provide more informative print as the lar is scanned.
k8 north: needed reset_test.c from v2, fixes to raminit.c
arch/x86
Kconfig: new CONFIG variable CBMEMK, meaning coreboot mem k, memory
used for coreboot.
init_cpus.c: functions to start up CPUs
stage1_mtrr.c: bring over early mtrr support from v2.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@847 f3766cd6-281f-0410-b1cd-43a5c92072e9
what you get are warnings.
There is lots of room for improvement as we move to all CAR
code, but that will take time.
I hope to get this to really compile over the weekend.
At the same time, if anybody wants to take a crack at it, your efforts
are welcome.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@843 f3766cd6-281f-0410-b1cd-43a5c92072e9
legacy. Use constants as much as possible instead of magic numbers. Set
up common prototypes in an include file.
The fidvid needs major cleanup but this code is so tricky I don't want
to start cleanup until I feel it is more or less working.
Signed-off-by: Ronald G. minnich <rminnich@gmail.com>
Acked-by: Ronald G. minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@841 f3766cd6-281f-0410-b1cd-43a5c92072e9
We need the sys_info struct in the global variables struct for
cache as ram on k8. The sys_info struct is generally very useful
so it makes sense to start accomodating it.
This patch adds an (empty for now) sys_info struct for geode.
It add sys_info to the global variables struct.
It removes global variables from console.h to a new file,
globalvars.h. Very little code needs to include this file.
This patch is tested on the dbe62 and simnow with no problems.
k8 compilation is now broken but I'm working on it. I'm going through
the eyeballs-bleed code on k8 startup to document it and with any luck
we'll have more functionality by the end of today. But it's hard ...
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@828 f3766cd6-281f-0410-b1cd-43a5c92072e9
This means that basic resource maps are working, initial hypertransport
setup is working, the amd8111 ISA device is working, config space is
working for all the parts, we can grow the FLASH part address space to
more than 64k, and in general we're having a good time.
Here is the output:
coreboot-3.0.824 Tue Aug 26 22:18:21 PDT 2008 starting...
(console_loglevel=8)
Choosing fallback boot.
LAR: Attempting to open 'fallback/initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: normal/option_table@0xfff80000, size 1776
LAR: normal/initram/segment0@0xfff80740, size 24404
LAR: normal/stage2/segment0@0xfff866f0, size 1
LAR: normal/stage2/segment1@0xfff86750, size 18542
LAR: normal/stage2/segment2@0xfff8b010, size 559
LAR: normal/payload/segment0@0xfff8b290, size 18142
LAR: bootblock@0xffff7fc0, size 32768
LAR: File not found!
LAR: Run file fallback/initram/segment0 failed: No such file.
Fallback failed. Try normal boot
LAR: Attempting to open 'normal/initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: normal/option_table@0xfff80000, size 1776
LAR: normal/initram/segment0@0xfff80740, size 24404
LAR: CHECK normal/initram/segment0 @ 0xfff80740
start 0xfff80790 len 24404 reallen 24404 compression 0 entry 0x00000004
loadaddress 0x00000000
Entry point is 0xfff80794
Hi there from stage1
stage1 returns
run_file returns with 0
Goal for tomorrow is to get initram done.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@826 f3766cd6-281f-0410-b1cd-43a5c92072e9
2. add support for same, brought over from v2.
Still no luck on 8111 ISA however. What are we missing?
The symptom is simple: Device 0:b.0 does not appear in the PCI list, so
device with vid/did 1022/7468 is not there, so we can not enable 5 MiB
flash addressing.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@824 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@818 f3766cd6-281f-0410-b1cd-43a5c92072e9
Remove pcspeaker until I can resolve space issues. Nobody was using it
anyway as it happens. It will go back in as soon as we
1. grow stage1 or
2. reconfigure it again
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@816 f3766cd6-281f-0410-b1cd-43a5c92072e9
Builds both K8 and Geode bioses with no trouble.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnch <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@811 f3766cd6-281f-0410-b1cd-43a5c92072e9
next step is to fix up this:
LAR build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error
1
make: exit 2
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@809 f3766cd6-281f-0410-b1cd-43a5c92072e9
image, and fails:
LAR build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error
1
Next step is to get rid of all warnings that are not #warning.
Then it is on to simnow.
Anyone who wants to work on the warnings is most welcome to.
DBE62 still builds with no problems.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@808 f3766cd6-281f-0410-b1cd-43a5c92072e9
Geode still builds fine.
include/lib.h includes a new function, cycles(), which is a u64 and
architecture-defined. (Thanks, Plan 9, for a sensible idea).
All rdtsc removed in favor of cycles()
All other changes are k8 specific. None of these changes adversely
impact existing platforms AFAICT.
Goal is that by 31/8/8, we're testing on simnow.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@807 f3766cd6-281f-0410-b1cd-43a5c92072e9
code to use it. That makes the code more readable and also less
error-prone.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@805 f3766cd6-281f-0410-b1cd-43a5c92072e9
dqs timing file compiled in yet.
Per discussion with YingHai Lu, we are only going to support F2 and
later CPUs. This will simplify more code.
I realize this code needs work, but it is in v2, and cleanup will get
easier once we have the baseline.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@804 f3766cd6-281f-0410-b1cd-43a5c92072e9
(0xA0000-0xAFFFF) and text mode (0xB8000-0xBFFFF).
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@802 f3766cd6-281f-0410-b1cd-43a5c92072e9
This one is far from obvious, so let me explain:
Basically, *msrnames[] is an array of pointers (strings) and pointers
need relocation. That's why they end up in .data.rel.ro.local and make
lots of trouble.
This should fix the crash Ron was seeing when register name printing was
enabled.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@793 f3766cd6-281f-0410-b1cd-43a5c92072e9
Continue to upgrade northbridge for k8.
Add a new standard include (which is optional on some chipsets),
mainboard.h, which will define important mainboard constants that
1. do not belong in dts
2. do not belong in Kconfig
3. are so tightly tied down to the mainboard they should probably not be
visible, i.e. the value of the variable is defined by artwork on the
mainboard, such as the socket type.
This file resolves the long-standing question of where certain
mainboard-dependent, compile-time control variables belong.
We've not resolved this issue in two years so here's how
we're going to do it. The first use of this is in the definition of
CPU_SOCKET_TYPE, needed by the northbridge code.
These changes do not affect existing Geode builds (tested on DBE62).
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@792 f3766cd6-281f-0410-b1cd-43a5c92072e9
variables have to use the special framework or they won't work.
Found by my section correctness checker. Error message was:
CHECK stage0 (non-empty .data sections)
build/northbridge/amd/geodelx/geodelxinit.o:
geode_link_priority_table clock_gating_default
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@790 f3766cd6-281f-0410-b1cd-43a5c92072e9
It's all REV_F now and we're wasting time pretending otherwise. This
change simplifies the code and will continue to simplify the code.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@788 f3766cd6-281f-0410-b1cd-43a5c92072e9
Added a stepping enum to k8.h. This will allow us to do things like this:
if (cpu_stepping(node) < E0)
and so on instead of is_cpu_pre_e0_in_bsp or whatever it is.
Added and fixed Kconfig variables.
Broke out northbridge by function, so we can see what goes with what.
This tree still builds a working DBE62 coreboot that boots a kernel; no harm done to existing ports.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@781 f3766cd6-281f-0410-b1cd-43a5c92072e9
it. Since it was the only content of the i440bxemulation northbridge
Kconfig, kill that file as well.
The i440BX RAM size is determined from the dts and the chipset specified
size is ignored. Print a warning for that, especially because v2 uses
the chipset specified RAM size.
Build and boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@766 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@765 f3766cd6-281f-0410-b1cd-43a5c92072e9
northbridge.c is marked for deletion, so don't sit up waiting for it to come home.
pci functions are in pci.c
domain functions are in domain.c
cpu functions are in cpu.c; cpu.c may move in the future to, say, someplace like cpu/amd/k8.
common functions are in common.c
These are still not set up quite right. I used svn copy to create the new files.
Geode builds fine. Anybody want to guess why this happens on k8? It's not clear to me.
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c: At top level:
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:60: error: ‘pci_conf1_read_config8’ redeclared as different kind of symbol
include/device/pci_ops.h:33: error: previous definition of ‘pci_conf1_read_config8’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:66: error: ‘pci_conf1_read_config16’ redeclared as different kind of symbol
include/device/pci_ops.h:34: error: previous definition of ‘pci_conf1_read_config16’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:72: error: ‘pci_conf1_read_config32’ redeclared as different kind of symbol
include/device/pci_ops.h:35: error: previous definition of ‘pci_conf1_read_config32’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:78: error: ‘pci_conf1_write_config8’ redeclared as different kind of symbol
include/device/pci_ops.h:36: error: previous definition of ‘pci_conf1_write_config8’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:84: error: ‘pci_conf1_write_config16’ redeclared as different kind of symbol
include/device/pci_ops.h:37: error: previous definition of ‘pci_conf1_write_config16’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:90: error: ‘pci_conf1_write_config32’ redeclared as different kind of symbol
include/device/pci_ops.h:38: error: previous definition of ‘pci_conf1_write_config32’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:116: error: ‘pci_conf1_find_on_bus’ redeclared as different kind of symbol
include/device/pci_ops.h:39: error: previous definition of ‘pci_conf1_find_on_bus’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:151: error: ‘pci_conf1_find_device’ redeclared as different kind of symbol
include/device/pci_ops.h:40: error: previous definition of ‘pci_conf1_find_device’ was here
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@764 f3766cd6-281f-0410-b1cd-43a5c92072e9
This mirrors commit 3504 in coreboot v2.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@751 f3766cd6-281f-0410-b1cd-43a5c92072e9
Again, some of this is verbatim from v2, we can change the form later
please.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@749 f3766cd6-281f-0410-b1cd-43a5c92072e9
add back in empty stage chipset variable. It will be filled in
later.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@736 f3766cd6-281f-0410-b1cd-43a5c92072e9
readability. Move to anonymous unions.
Build tested on all targets. Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Ron tested this and it boots to Linux.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@730 f3766cd6-281f-0410-b1cd-43a5c92072e9
(1)we now compile in all printks, which is good: we can print any message provided we can change
the console log level at any time.
(2) The console log level is compiled in and unchangeable, which is bad, as it defeats the purpose of (1).
Add a BIOS_ALWAYS log level. Make console log level a variable. Make functions that set it and get it
visible everywhere. Always print out the version message; this is really *not* noise!
PCI: Simplify pci functions so that they can be used in stage1 or anywhere for that matter. Add
a find function which is needed for many stage1 functions. Note that we copy but also clean up
the libpayload stuff just a bit.
Get rid of config space type 2. If there was ever a platform that used it, I don't know what it was,
and the presence is a needless distraction.
tested and working on DBE62 (which means the console and the pci functions work :-).
There is a remaining problem with dumplxmsrs which nobody understands. It prints out garbage if we use the
%s for the msr names.
Formatting is an issue; if somebody wants to fix formatting they can assume I will ack it. Sorry,
my emacs has gone just nuts.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@729 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@722 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@721 f3766cd6-281f-0410-b1cd-43a5c92072e9
Resource map and a way to use the pci config stuff from stage 1, done in
a way that will work in stage 2 (but only for systems that use type 1
config cycles; will fail for type MEM config cycles).
We need to rethink the PCI config stuff per Stepan's comment, in part
because the device tree now includes things that are NOT PCI devices.
Stepan's suggestion, to make the functions take busdevfn as the
parameter, makes a lot of sense.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.s
git-svn-id: svn://coreboot.org/repository/coreboot-v3@720 f3766cd6-281f-0410-b1cd-43a5c92072e9
it working, then we'll get it pretty.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@717 f3766cd6-281f-0410-b1cd-43a5c92072e9
Also, per Uwe, remove the \r\n for \n
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@715 f3766cd6-281f-0410-b1cd-43a5c92072e9
This creates a clearer distinction between source files in the source
tree we want to have compiled and indirectly created object/source files
in the object tree.
It also will make enable us to move to whole-program
optimization/compilation which should yield substantial size savings.
Then again, we may be able to do that without the makefile conversion as
well.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@714 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is not nearly complete, but just the current state of my tree.
k8/raminit.c does not compile at all. Lots of fixes are still needed to bring
it working into v3. I've gone through about 1/8 of the file, it errors out on
line 576 now.
The mcp55 files are in a very early state and also do not compile for me, so
I've disabled them by commenting out the select in mainboard/gigabyte/Kconfig.
Once northbridge/amd/k8/raminit.c builds, k8_ops needs to be added, then we
may actually see the first v3 k8 build. :)
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@713 f3766cd6-281f-0410-b1cd-43a5c92072e9
debug routine. Use them for printout.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@708 f3766cd6-281f-0410-b1cd-43a5c92072e9
understandable. Added benefit is complaining loudly for
unsupported 2 GB DIMM size.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested on the dbe62 up to and including Etherboot.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@671 f3766cd6-281f-0410-b1cd-43a5c92072e9
mathematically impossible condition of a value being above and below the
specified range at the same time. Change it to check for out-of-range.
arch/x86/geodelx/geodelx.c:set_delay_control() is missing a break, it
will keep going and mess up DRAM timings.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Both changes look right to me.
Acked-by: Marc Jones <marc.jones@amd.com>
The raminit in v2 was fixed in r2899 | rminnich | 2007-10-26 with this
log:
> The lxraminit change fixes a bug (&& used instead of ||) [...]
> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
> Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@659 f3766cd6-281f-0410-b1cd-43a5c92072e9
