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This finishes the fix to log2. The computed dram size now matches the

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size indicated by byte 31 of SPD. 

Memory is still not working; hanging in dqs training. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@854 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-09-01 02:44:08 +00:00
commit 9cdd8a9d67
5 changed files with 23 additions and 21 deletions
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2
northbridge/amd/k8/coherent_ht.c
View file

@ -322,7 +322,7 @@ int optimize_connection(u32 node1, u8 link1, u32 node2, u8 link2)
freq_cap2 = read_freq_cap(node2, link2 + PCI_HT_CAP_HOST_FREQ_CAP);
/* Calculate the highest possible frequency */
freq = log2(freq_cap1 & freq_cap2);
freq = log2c(freq_cap1 & freq_cap2);
/* See if I am changing the link freqency */
old_freq = pci_conf1_read_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ);

2
northbridge/amd/k8/incoherent_ht.c
View file

@ -229,7 +229,7 @@ static int ht_optimize_link(
freq_cap2 = ht_read_freq_cap(bdf2, pos2 + LINK_FREQ_CAP(offs2));
/* Calculate the highest possible frequency */
freq = log2(freq_cap1 & freq_cap2);
freq = log2c(freq_cap1 & freq_cap2);
/* See if I am changing the link freqency */
old_freq = pci_conf1_read_config8(bdf1, pos1 + LINK_FREQ(offs1));

12
northbridge/amd/k8/pci.c
View file

@ -332,8 +332,8 @@ static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned
if (resource) {
resource->base = 0;
resource->size = 0;
resource->align = log2(HT_IO_HOST_ALIGN);
resource->gran = log2(HT_IO_HOST_ALIGN);
resource->align = log2c(HT_IO_HOST_ALIGN);
resource->gran = log2c(HT_IO_HOST_ALIGN);
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
compute_allocate_resource(&dev->link[link], resource,
@ -345,8 +345,8 @@ static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned
if (resource) {
resource->base = 0;
resource->size = 0;
resource->align = log2(HT_MEM_HOST_ALIGN);
resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->align = log2c(HT_MEM_HOST_ALIGN);
resource->gran = log2c(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
compute_allocate_resource(&dev->link[link], resource,
@ -359,8 +359,8 @@ static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned
if (resource) {
resource->base = 0;
resource->size = 0;
resource->align = log2(HT_MEM_HOST_ALIGN);
resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->align = log2c(HT_MEM_HOST_ALIGN);
resource->gran = log2c(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM;
compute_allocate_resource(&dev->link[link], resource,

24
northbridge/amd/k8/raminit.c
View file

@ -31,7 +31,7 @@
#include <string.h>
#include <mtrr.h>
#include <macros.h>
#include <spd.h>
#include <spd_ddr2.h>
#include <cpu.h>
#include <msr.h>
#include <amd/k8/k8.h>
@ -765,7 +765,7 @@ void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
value = spd_read_byte(device, SPD_BANK_NUM); /* banks */
if (value < 0) goto hw_err;
if ((value & 0xff) == 0) goto val_err;
sz->bank = log2(value & 0xff); // convert 4 to 2, and 8 to 3
sz->bank = log2c(value & 0xff); // convert 4 to 2, and 8 to 3
printk(BIOS_SPEW, "%d SPD banks %d bank\n", value, sz->bank);
sz->per_rank += sz->bank;
printk(BIOS_SPEW, "sz->per_rank is now %d\n", sz->per_rank);
@ -774,8 +774,9 @@ void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
if (value < 0) goto hw_err;
value &= 0xff;
if ((value != 72) && (value != 64)) goto val_err;
sz->per_rank += log2(value) - 3; //64 bit So another 3 lines
printk(BIOS_SPEW, "value %d log2(value) %d sz->per_rank now %d\n", value, log2(value), sz->per_rank);
/* why log2f (floor) here? because 72 bits is really 64 bits + parity */
sz->per_rank += log2f(value) - 3; //64 bit So another 3 lines
printk(BIOS_SPEW, "value %d log2f(value) %d sz->per_rank now %d\n", value, log2f(value), sz->per_rank);
/* How many ranks? */
value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK); /* number of physical banks */
@ -783,7 +784,7 @@ void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
// value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT;
value &= SPD_MOD_ATTRIB_RANK_NUM_MASK;
value += SPD_MOD_ATTRIB_RANK_NUM_BASE; // 0-->1, 1-->2, 3-->4
printk(BIOS_SPEW, "# banks %d\n", value);
printk(BIOS_SPEW, "# ranks %d\n", value);
/*
rank == 1 only one rank or say one side
rank == 2 two side , and two ranks
@ -802,13 +803,14 @@ void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
if (value < 0) goto hw_err;
value &= 0xff;
printk(BIOS_SPEW, "spd rank size is %d\n", value);
value = log2(value);
value = log2f(value);
if(value <=4 ) value += 8; // add back to 1G to high
value += (27-5); // make 128MB to the real lines
printk(BIOS_SPEW, " computed value is %d\n", value);
if( value != (sz->per_rank)) {
printk(BIOS_ERR, "Bad RANK Size -- value is 0x%x, and it should be 0x%x\n", value, sz->per_rank);
goto val_err;
printk(BIOS_ERR, "This error has been reduced to a warning for now\n");
// goto val_err;
}
goto out;
@ -1112,7 +1114,7 @@ unsigned long interleave_chip_selects(const struct mem_controller *ctrl, int is_
/* Chip selects can only be interleaved when there is
* more than one and their is a power of two of them.
*/
bits = log2(chip_selects);
bits = log2c(chip_selects);
if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) { //chip_selects max = 8
return 0;
}
@ -1643,7 +1645,7 @@ struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, l
printk(BIOS_DEBUG, "%s: 0x%x\n", "i:", i);
printk(BIOS_DEBUG, "%s: 0x%x\n", "\tlatencies:", latencies);
/* Compute the lowest cas latency supported */
latency = log2(latencies) - 2;
latency = log2f(latencies) - 2;
/* Loop through and find a fast clock with a low latency */
for(index = 0; index < 3; index++, latency++) {
@ -1716,7 +1718,7 @@ struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, l
}
/* Compute the lowest cas latency supported */
latency = log2(latencies) -2;
latency = log2f(latencies) -2;
/* Walk through searching for the selected latency */
for(index = 0; index < 3; index++, latency++) {
@ -1832,7 +1834,7 @@ int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *
return -1;
}
value = 6 - log2(value); //4-->4, 8-->3, 16-->2
value = 6 - log2f(value); //4-->4, 8-->3, 16-->2
clocks = meminfo->sz[i].per_rank - 27 + 2 - value;

4
southbridge/amd/amd8111/acpi.c
View file

@ -185,8 +185,8 @@ static void acpi_read_resources(struct device * dev)
resource = new_resource(dev, 0x58);
resource->base = 0;
resource->size = 256;
resource->align = log2(256);
resource->gran = log2(256);
resource->align = log2f(256);
resource->gran = log2f(256);
resource->limit = 65536;
resource->flags = IORESOURCE_IO;
resource->index = 0x58;