northbridge/amd/geodelx/raminit.c:auto_size_dimm() checks for the

mathematically impossible condition of a value being above and below the
specified range at the same time. Change it to check for out-of-range.
arch/x86/geodelx/geodelx.c:set_delay_control() is missing a break, it
will keep going and mess up DRAM timings.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Both changes look right to me.
Acked-by: Marc Jones <marc.jones@amd.com>


The raminit in v2 was fixed in r2899 | rminnich | 2007-10-26 with this
log:
> The lxraminit change fixes a bug (&& used instead of ||) [...]
> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
> Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@659 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Carl-Daniel Hailfinger 2008-04-16 16:40:45 +00:00
commit 5a19770667
2 changed files with 3 additions and 2 deletions

View file

@ -386,6 +386,7 @@ static void set_delay_control(u8 dimm0, u8 dimm1)
msr.hi |= delay_control_table[i].fast_hi;
msr.lo |= delay_control_table[i].fast_low;
}
break;
}
}
wrmsr(GLCP_DELAY_CONTROLS, msr);

View file

@ -113,7 +113,7 @@ static void auto_size_dimm(unsigned int dimm, u8 dimm0, u8 dimm1)
/* EEPROM byte usage: (5) Number of DIMM Banks */
banner(BIOS_DEBUG, "MODBANKS");
spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) {
if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
printk(BIOS_EMERG, "Number of module banks not compatible\n");
post_code(ERROR_BANK_SET);
hlt();
@ -124,7 +124,7 @@ static void auto_size_dimm(unsigned int dimm, u8 dimm0, u8 dimm1)
/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
banner(BIOS_DEBUG, "FIELDBANKS");
spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) {
if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
printk(BIOS_EMERG, "Number of device banks not compatible\n");
post_code(ERROR_BANK_SET);
hlt();