There is no reason I can think to also pass the old object into the
constructor considering that the new objects contains the exact same
contents during that call (it's copied over a few lines above).
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Idd5b34134b6064c19266448b551248eb29e097fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89957
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add a mechanism for mainboards to override default values of CFR
objects defined in SoC or common code without duplicating object
metadata.
Mainboards can now declare a simple override table mapping option
names to new default values:
const struct cfr_default_override mb_cfr_overrides[] = {
CFR_OVERRIDE_BOOL("s0ix_enable", false),
CFR_OVERRIDE_ENUM("pciexp_aspm", ASPM_DISABLE),
CFR_OVERRIDE_END
};
The CFR backend checks this table when writing options and uses the
override value if one exists. All other metadata (name, help text,
enum values, flags) comes from the original object.
Change-Id: Ifb3da90d605f2799bf0207ff58d69bee3415ccc2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89933
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Document the ACPI thermal zone pattern used across multiple mainboards
that implement five-level fan control via power resource state machines.
This pattern is used by 9 mainboards including Google Chromebooks
(beltino, jecht variants), Samsung stumpy, and Intel reference boards
(wtm2, baskingridge, emeraldlake2).
The documentation covers:
- Power resource state machine implementation
- Temperature management via PECI/SuperIO
- Active and passive cooling policies
- Critical FNP4._OFF no-op requirement for Windows compatibility
- Implementation variations and checklist for new boards
Initial framework generated by Cursor AI, heavily edited thereafter.
Change-Id: I4174a4552c97fb85a894f5362948d57057cacb81
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The documentation has been adjusted to include additional variants,
and brushed up a bit for clarity.
Change-Id: Ia7711d5105e568113de219b1aa43e3a5d50aaf9c
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Unlike already implemented Keyboard Controller Style (KCS) interface
Block Transfer interface is not byte-oriented and implies that device is
capable of buffering a command before processing it. Another difference
is that polling can be replaced with interrupts, though this isn't used
by this implementation.
More details can be found in "Intelligent Platform Management Interface
Specification", v2.0, Rev. 1.1:
https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-intelligent-platform-mgt-interface-spec-2nd-gen-v2-0-spec-update.pdf
This was initially tested on Talos II (OpenPower platform) by Raptor
Computing Systems. Later versions were tested using QEMU and ipmi_sim
from OpenIPMI project as well as QEMU's builtin BMC simulator.
Change-Id: Idb67972d1c38bbae04c7b4de3405350c229a05b9
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67057
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The document is no longer accessible at the original URL.
Change-Id: I9601b3fb9a86796dafd742961d3d130fb735804e
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89463
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This updates the statistics for actual release tag.
Change-Id: I84116caa35be2df28372dd4293ad73eb13ec9dd4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
coreboot 24.12, 24.08, and 4.21 have already been released, so the
"Upcoming release" text in their titles is outdated and unnecessary.
Change-Id: I19cb5585c838c64366e057ceeaf0a18e01372bfe
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This port adds support for the ASUS PRIME H610i-PLUS D4, a Mini-ITX
LGA1700 motherboard with the H610 chipset. I have been using this
port on one of these boards as my primary workstation for around
the last month, and it generally works well apart from a lack of S3
sleep. I have not yet managed to figure out the issue with that,
and have been using suspend-to-disk instead.
This board is highly similar to the H610M-K ported by Mate Kukri in
#84243, and I have included the NCT6798D fan control setup from
that patchset with minimal modification.
Working:
- Console over onboard serial port
- PS/2 keyboard
- Port 80 POST codes over ASUS debug header
- All USB ports, including USB3 working, except front USB2
- All outputs (DP, HDMI, VGA) for iGPU
- M.2 slot
- PCIe WiFi card in WiFi slot
- Onboard Ethernet
- PCIe ASPM and clock power management for all devices
- x16 PCIe slot
- All SATA ports
- Hard drive indicator LED
- All audio including front panel
- Fan control
- ME disable with HAP bit in IFD
- HSPHY-in-FMAP when ME is disabled
Untested:
- CNVi WiFi card in WiFi slot
- Front USB2 ports (did not have an adapter on hand to test)
- Status LEDs in actual error states (they do show a normal status
normally)
Not working:
- S3 sleep
Change-Id: Ib2dd2916be06dc515863df85ecb06ec043a9bc6e
Signed-off-by: Dodoid <git-noreply@dodoid.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These are the preliminary release notes. They'll need to be updated
with any changes done this week. We'll need another patch after the tag
to capture the final statistics. The notes will be changed from
"Upcoming release" after the tag is done.
Change-Id: I0b4a1ad351a5772059061837a32d3d8a08c43885
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89283
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generated by util/vboot_list/vboot_list.sh.
Change-Id: I313b9a59b9a009257fa4a0969c91b334feb55b8b
Signed-off-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89354
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This adds the release notes template for the upcoming December release
of coreboot.
Change-Id: Iffaa625137f4edf994d73984d847b1cf926f8078
Signed-off-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89352
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
EDK2 driver for loading OpROMs have been merged into Matt's tree, and
should also be merged into main UefiPayloadPkg repo in upcoming
days/weeks.
With recent patches, DP and USB ports are working perfectly.
Change-Id: I9bef2c7e5a84660231abad9da69c0ec73e8b6507
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
This should address the following open action item from the coreboot
leadership meetings[1]:
> Add clarification to docs, "do not use gerrit change-id or CB: format
> in reference to already-merged patches".
[1] https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/YCA55MINAFK5M56OAUA2NMM7WDMDEGXI/
Change-Id: Ie742caca70e284254bb7f8a070c3a441b6a80c58
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88776
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Several files use embedded reStructuredText blocks in order to use the
:doc: directive to reference other markdown files using a relative path.
MyST Parser supports a similar feature using the standard Markdown
autolink (angled bracket) syntax, so use this instead as it is cleaner.
Both methods use the first heading of the linked file as the text shown
in the reference, though MyST Parser also supports the standard [link
text](../path/to/file.md) syntax to explicitly set the link text.
Note that when using the autolink syntax, `project:` must be prepended
to the relative path as it expects a URI scheme for all autolinks. This
is not required when using the separate text and URI syntax.
Before:
```{eval-rst}
Example text :doc:`../relative/path`.
```
After:
Example text <project:../relative/path.md>
Using the Markdown syntax also avoids formatting issues if any plain
text in the eval-rst block uses Markdown formatting syntax where they
would unintentionally be parsed differently due to text being parsed as
reStructuredText.
Some :doc: instances still remain as they are used within reST style
tables in an eval-rst block, so these were left as is since the Markdown
syntax would be invalid in that context.
[1]: https://myst-parser.readthedocs.io/en/latest/syntax/cross-referencing.html#autolinks
Change-Id: I8828bf7efe13de6d6f628f6b64151fbd25289fa5
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Since the boot flow is different on AMD compared to other x86
platforms document what is done and where.
Explain that AMDCOMPRESS does more than compressing the input.
It also parses the input as an ELF and extracts the first PT_LOAD marked
area from it and discards all other information from the ELF.
Explain bootblock.bin generation and that it has not much to do
with bootblock.elf, unlike on other platforms.
While on it also fix a whitespace in the following line.
Change-Id: Ida763f879c133be54ea1ca2abd3059db0d2c1ef7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87316
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Update the example, after the short multi-line comment alternative was
added several years ago, when the Wiki was still used.
Change-Id: I401180a9ac7c7cdc45fb8e9ba364823092cea6da
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Add a heading for Skylake/Kabylake Lenovo mainboards in anticipation
of additional boards being added in the future. Add a new page for the
T480/T480s, loosely based on the page for the T440p.
Thanks to Askareth on Matrix for the initial draft and copious testing.
Change-Id: I3c7a9ca28be5524b42177b92387f35c6d25b48da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88439
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change incorporates the final statistics for the 26.06 release and
changes it from upcoming to the final version of the notes.
- Add a section for Project Updates
- Update the introduction, removing the comment about GCC 15, which was
a bit confusing. We can now build the toolchain with GCC 15, but it is
not yet part of the toolchain.
Change-Id: I27defefacdf8b3a826c801da051e3218394f81e2
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88312
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Rephrase some items
- Add additional code examples
- Add additional sections
- Update documentation to the current state of the codebase.
Change-Id: I6e4cc244edf6cc860cc66165173f134a30a81589
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
A compaq_8300_elite_sff build can run on these models mostly unmodified.
Spawn a new variant from it, tie up some obvious loose ends and bring it
officially into the fold.
BUG=https://ticket.coreboot.org/issues/581
Change-Id: Ic0f04d586a8361968d7f6c3e3d048f945528cb84
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
These are the release notes planned to go out with the 25.06 release.
Note that we've removed the bugs section. We may look at adding
"Fixed Bugs" and "New Bugs" in the future, but it was depressing not
seeing changes between the releases.
Change-Id: I8cedbdb7b05605d1904446590fb25552a7e0c727
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88206
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The old wiki no longer exists (see the announcement at [1]), the
current URLs lead to an HTTP 404.
To fix it, replace the URLs with the main page URL, which contains
links to the current documentation, manual, etc.
[1]: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/GNT23GQEQ5I5JCJ6YKUSRXD7JORSG4RV/
Change-Id: Ifb430a033d12f8064893f75315d577b5e78ffc9e
Signed-off-by: Raphaël Mélotte <raphael.melotte@mind.be>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
This adds the release notes template for the upcoming September release
of coreboot.
Change-Id: I9033b107f148b4b40bb1243d2d0eb0b7e7f7b6dc
Signed-off-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
- Clean up section on flashrom vs flashprog
- Clarify flash regions and command used to flash `bios` region only
- Specify command used for external flashing
Change-Id: Icf464f4532b956731040fed97da0726856524c16
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently the SMMSTOREv2 only supports MMIO ROM below 4GiB. As the
space below 4GiB is typically limited on x86, add support for extended
MMIO ROM windows as found on recent hardware.
Allow the SMMSTOREv2 to be memory mapped above 4GiB by adding a new
field to the coreboot table called 'mmap_addr'. The users outside
of coreboot must check the size field of the coreboot struct to
determine if mmap_addr is supported. When it is it holds the
64-bit physical address to the MMIO ROM window.
The old 'mmap_addr' was renamed to 'mmap_addr_deprecated' to indicate
that it should not be used any more.
Change-Id: I1131cfa5cdbf92bbd33de3e5b22a305136eec9f7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87114
Reviewed-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Use an additional Realtek NIC MAC programming sequence recently
added to drivers/net/r8168.c.
BUG=https://ticket.coreboot.org/issues/579
TEST=Specified MAC address now recognized and retained by Linux r8169
driver without further work.
Change-Id: Ia1409874920b2e598e8b8b3c186fc46bd0cef296
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87437
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With DRIVERS_EFI_UPDATE_CAPSULES enabled and when at least one capsule
was found, SMMSTORE SMI handler can use commands with the highest
bit (0x80) set to access the whole flash instead of just the SMMSTORE
region. The rest of the interface is identical to regular SMMSTORE v2
except for a new call to control full flash access.
The added call saves information about the availability of capsules in
SMM memory. The call is ignored when run more than once, meaning there
should be no way of enabling full flash handling after it was disabled
and vice versa. The call should always be made by the firmware to lock
further calls, so that an OS could not gain full flash access. This is
done on entry to BS_POST_DEVICE after capsules are obtained in
BS_DEV_INIT.
Change-Id: I7f3dbfa965b9dcbade8b2f06a5bd2ac1345c7972
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
- some formatting fixes;
- add information about proprietary blobs;
- update information about the tested hardware and operating systems.
Change-Id: I85a8f1df2ffc6e0e1674c4b82888a3964aa8d672
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
- Update the instructions for building the documentation to account for
the switch from Recommonmark to MyST Parser
- Update outdated URLs
- Update various details to account for the current behavior and
features resulting from previous changes
Change-Id: I569862e30fb88a421ad2338aafabeaf3ea76836a
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
According to MediaTek's proprietary PI_IMG parser, two cookies (one
header and one footer) are expected. Therefore, add a script to perform
validity check of the PI_IMG firmware, so that format errors could be
caught in build time.
Change-Id: I27011492c7fab747aa3ee12d514d20a6a52d0a4d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87226
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To allow adding more scripts to the util/mtkheader folder, rename it to
util/mediatek. Also update description.md and regenerate
Documentation/util.md and util/README.md by util_readme.sh.
Change-Id: Ibc6ef9dddc541d2dd471898af431cadde231edca
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
As CB:71757 [1] updates Documentation/util.md and util/README.md
manually without modifying util/intelp2m/description.md, we port the
description changes back to that file.
[1] commit da54bd60af ("Documentation: Update information about
intelp2m")
Change-Id: I3d3f87517c445d650e9cea61448b28d005d46737
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87224
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This doesn't change any text - it just reformats the existing document.
- reflow paragraphs to 72 characters
- Put examples inside pre-formatted text blocks
- Adds spacing before section markers
Change-Id: I83925a4469e264da5887334e2584466cef089503
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
coreboot supports more than just one PCI segment group by having more
than one domain in the devicetree, so update the PCI device description.
Change-Id: I9911b5e43732dd32638d540fcec6ca57b34d4fbc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87206
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Even when the identifier of an I2C device doesn't have a '0x' prefix,
it's still interpreted as a hexadecimal number.
Change-Id: I0e5a7e39ac56e25499493a16eefa49e4f8d79337
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
In contracts to the ISA and LPC bus, eSPI doesn't support legacy
ISA-style DMA any more, so don't list eSPI as interface in the 'drq'
chapter.
The Intel document #841685 "Enhanced Serial Peripheral Interface (eSPI)
Interface Base Specification (for Client and Server Platforms)" revision
1.6 says this about the eSPI interface: "However, 8237 DMA and Firmware
Hub (FWH) are not supported over this interface."
Change-Id: I69d4b09688699dfc984a42671abfe3804d30ade9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87204
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
