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Documentation: mb/erying/tgl: Update documentation

Browse source 
EDK2 driver for loading OpROMs have been merged into Matt's tree, and
should also be merged into main UefiPayloadPkg repo in upcoming
days/weeks.

With recent patches, DP and USB ports are working perfectly.

Change-Id: I9bef2c7e5a84660231abad9da69c0ec73e8b6507
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
This commit is contained in:
Alicja Michalska 2025-08-08 05:57:13 +02:00 • committed by David Hendricks
commit 7e73d4ef30
1 changed files with 27 additions and 48 deletions
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75
Documentation/mainboard/erying/tgl/tgl_matx.md
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@ -20,29 +20,23 @@ To build full working image of coreboot, the following blobs are required:
+-----------------+---------------------------------+----------------------+
```
Microcode for those SoCs cannot be generated from the tree.
While boards with D1 (production) stepping may work, microcode Intel had
included in their tree is too old, which causes issues with APIC
(Advanced Programmable Interrupt Controller), resulting in overall instability.
Microcode for D0 stepping cannot be generated from the tree.
Therefore, including external microcode is **mandatory** for boards sold with
D0 stepping (Engineering Sample).
This is **required** for boards sold with D0 SoC revision (Engineering Sample).
Maintainer of this port had included publicly-available [microcodes] in
`3rdparty/blobs` coreboot repository, which are being pulled as submodule.
To choose appropriate microcode for your system, you should choose:
1. If your motherboard uses Engineering Sample (D0) stepping:
- `cpu806D0_platC2_ver00000054_2021-05-07_PRD_B0F9E245.bin`
2. If your motherboard uses retail (D1) stepping:
- `cpu806D1_platC2_ver00000046_2023-02-27_PRD_08E6188A.bin`
Microcode binary for D0 stepping is called
`cpu806D0_platC2_ver00000054_2021-05-07_PRD_B0F9E245.bin`.
By going to `Chipset -> Include CPU microcode in CBFS
(Include external microcode binary)`
It should be selected by going to:
`Chipset -> Include CPU microcode in CBFS (Include external microcode binary)`.
Failure to choose an appropriate microcode may result in:
- Bricked (unbootable) board
- Issues with APIC, resulting in random freezes
- MCE (Machine Check Exception) errors
- Unstable system RAM, leading to bit flips and data corruption
Failure to choose an appropriate microcode will result in:
- MCE (Machine Check Exception) errors.
- Issues with APIC, resulting in random hangs.
- Unstable system RAM, leading to bit flips and data corruption.
There are no extra steps required for FSP.
Both SKUs work perfectly with FSP Intel publishes in their public repository.
@ -88,7 +82,7 @@ despite using mobile SoC and PCH.
- RS232 serial output from IT8613E for debugging (cbmem, Linux)
- Fan control from userspace (IT8613E Environment Controller)
- USB2.0 and 3.0
- HDMI (iGPU, including audio)
- HDMI, DisplayPort (iGPU, including audio)
- Realtek RTL8111 (GbE NIC)
- Realtek ALC897 (integrated audio)
- PCIe x16 4.0 (SoC)
@ -106,19 +100,14 @@ despite using mobile SoC and PCH.
- XMP Profiles (some people reported issues, despite successful tests).
You can enable it by setting `SpdProfileSelected` in `romstage_fsp_params.c`.
See [FSP XMP flags] for configuration options, proceed with caution.
- GOP init on external GPUs (most EDK2 branches do not include module
necessary to load external Option ROMs)
- Sleep states (which were broken on stock as well)
- USB3.2 might take few tries to get detected at full speed
- iGPU DisplayPort (very simple fix, did not have time to fix GPIO)
- Automatic fan control (fans will always spin at 50% - see below)
- 2x USB2.0 FP and M.2 NGFF USB2.0 not mapped (yet)
- PCIe ASPM (results in AER spam in dmesg)
- Sleep states (which were broken on stock as well, RAM loses power in S3).
- Automatic fan control (fans will always spin at 50% - see below).
- PCIe ASPM (results in AER spam in dmesg).
Please ensure to:
- Disable sleep state in your OS to prevent data loss
- Disable sleep state in your OS.
- Configure automatic fan control using pwmconfig
(`modprobe it87 force_id=0x8603`)
(`modprobe it87 force_id=0x8603`).
- Append `pcie_aspm=off` to your kernel commandline to avoid dmesg spam.
## Notes
@ -126,7 +115,7 @@ Please ensure to:
1. Required blobs, if flashing the entire flash chip.
They can be skipped safely if you are planning on flashing
only the `SI_BIOS` region.
- Intel Flash Descriptor (IFD): `descriptor.bin`
- Intel Flash Descriptor (IFD): `fd.bin`
- Intel Management Engine (ME): `me.bin`
Both blobs included in `3rdparty/blobs` repository were extracted
@ -151,29 +140,21 @@ Please ensure to:
- U-Boot
- LinuxBoot (U-Root + Linux kernel)
If you would like to see output on your iGPU before that stage
(for picking a different boot medium or toggling Secure Boot setting),
you need to use [MrChromebox's EDK2] fork and include [GOP driver] for
TigerLake iGPU in your build.
This will allow you to see output of EDK2 (payload, boot picker)
on your monitor connected to iGPU.
If you're planning to primarly use an external card, disable iGPU by
enabling `Chipset -> Disable Integrated GFX Controller (0:2:0)`
and use [elly's EDK2] tree.
and use [MrChromebox's EDK2] tree.
In order to enable loading Option ROMs from PCIe devices, go to:
`Payload -> edk2 additional custom build parameters`
and add the string: `-D LOAD_OPTION_ROMS=TRUE`
In order to enable loading Option ROMs from PCIe devices, enable:
`Payload -> Load and Execute OpROMs on PCIe devices`
This functionality has been tested with following graphics cards,
with following results:
- Nvidia GeForce RTX3080, RTX3090: Works perfectly
- AMD Radeon RX6600XT, RX7800XT: Works with ReBAR disabled,
no output in EDK2 with ReBAR enabled
- Intel Arc A580: Works with ReBAR disabled,
corrupted framebuffer before modprobing with ReBAR enabled
- Nvidia GeForce RTX3080, RTX3090: Works perfectly.
- AMD Radeon RX6600XT, RX7800XT: Works, but requires
`Extend resource window for PCIe devices above 4G` if `Support PCIe
Resizable BARs` is enabled.
- Intel Arc A580: Works, but option
`Extend resource window for PCIe devices above 4G` is **mandatory**.
## Specification
@ -197,7 +178,5 @@ corrupted framebuffer before modprobing with ReBAR enabled
[microcodes]: https://github.com/platomav/CPUMicrocodes/tree/master/Intel
[FSP XMP Flags]: https://github.com/intel/FSP/blob/master/TigerLakeFspBinPkg/Client/Include/FspmUpd.h#L586-L591
[MrChromebox's EDK2]: https://github.com/MrChromebox/edk2
[elly's EDK2]: https://github.com/ellyq/edk2
[GOP driver]: https://github.com/MrChromebox/blobs/blob/master/soc/intel/tgl/IntelGopDriver.efi
[flashrom]: https://flashrom.org/
[flashprog]: https://flashprog.org/wiki/Flashprog