Commit graph

20,321 commits

Author SHA1 Message Date
Lee Leahy
bbffc9c0ec UPSTREAM: src/lib: Fix spacing
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: spaces required around that '?' (ctx:WxV)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '<' (ctx:VxV)
ERROR: spaces required around that '+=' (ctx:VxV)
ERROR: space required after that ',' (ctx:VxV)
ERROR: space required before the open brace '{'
ERROR: space required after that close brace '}'
ERROR: need consistent spacing around '+' (ctx:WxV)
ERROR: need consistent spacing around '*' (ctx:WxV)
ERROR: need consistent spacing around '&' (ctx:VxW)
ERROR: spaces required around that '?' (ctx:VxW)
ERROR: spaces required around that ':' (ctx:VxW)
ERROR: trailing whitespace
ERROR: space prohibited before that '++' (ctx:WxO)
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: space prohibited after that '!' (ctx:BxW)
ERROR: spaces prohibited around that '->' (ctx:VxW)
ERROR: space prohibited after that '-' (ctx:WxW)
WARNING: space prohibited before semicolon
WARNING: unnecessary whitespace before a quoted newline
WARNING: missing space after return type

Note that lib/libgcov.c and lib/lzmadecode.c are providing false
positives for ERROR: need consistent spacing around '*' (ctx:WxV)
An example is:
void __gcov_merge_add(gcov_type *counters  __attribute__ ((unused)),
      unsigned int n_counters __attribute__ ((unused))) {}

TEST=Build and run on Galileo Gen2

Change-Id: I8cf3e68b6faf23fdda2975f4a36acb783e2f5727
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 35af5c47b0
Original-Change-Id: I0016327a5754018eaeb25bedf42338291632c7c1
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18733
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454544
2017-03-14 07:25:24 -07:00
Nicola Corna
ecc4ace061 UPSTREAM: nvramcui: Add USB support
Enable the USB during the initialization of nvramcui. Without it
the USB keyboards don't work, which makes this payload pointless
on the systems where a PS/2 keyboard port isn't available.

Based on https://review.coreboot.org/#/c/17507/

BUG=none
BRANCH=none
TEST=none

Change-Id: I794d780072cdd36c98b2dac0012ecb69c1d609e2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fece39baa5
Original-Change-Id: I04697c5f582b41e6f6ffe98955bf59f4fe57f66e
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18765
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/454543
2017-03-14 07:25:23 -07:00
Nicola Corna
03908ec016 UPSTREAM: util/superiotool: Add support for Fintek F71808A
Default values taken from the datasheet and from the dump of
an uninitialized F71808A on a Sapphire Pure Platinum H61.

Both the control registers and the HWM configuration registers
are added.

BUG=none
BRANCH=none
TEST=none

Change-Id: I4e77c290805b8f3461bd46d7b7e252e7f552967c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fbd1aab33
Original-Change-Id: Ia6e2a7c13a5086d19ebdb426f2f975b43220a273
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18562
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/454542
2017-03-14 07:25:23 -07:00
Lee Leahy
2facdfb6c3 UPSTREAM: soc/intel/common: Remove parenthesis
Fix the following error detected by checkpatch.pl:

ERROR: return is not a function, parentheses are not required

TEST=Build and run on Galileo Gen2

Change-Id: Idf0dc83cec44a59369333d6bb3f44099d533278a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8fbd953ffb
Original-Change-Id: Idf7723d4fd48124a26bbb626afc310820f859f66
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18757
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454541
2017-03-14 07:25:22 -07:00
Lee Leahy
1331b9e6b9 UPSTREAM: soc/intel/common: Fix unsigned warnings
Fix the following warning detected by checkpatach.pl:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'

TEST=Build and run on Galileo Gen2

Change-Id: I4a4dc3bab94a5f6c1fd8ee691233a1e2d30ebc76
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 20727813bb
Original-Change-Id: Ic266c077eb115e0c7d934c15bcc4cc9b9e530a39
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18756
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454540
2017-03-14 07:25:22 -07:00
Lee Leahy
779eac7dd8 UPSTREAM: soc/intel/common: Fix spacing issues
Fix the following errors detected by checkpatch.pl:

ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that ':' (ctx:VxW)
ERROR: space required after that ',' (ctx:VxV)
ERROR: space required before the open parenthesis '('
ERROR: switch and case should be at the same indent
ERROR: "foo ** bar" should be "foo **bar"

TEST=Build and run on Galileo Gen2

Change-Id: I7dad3594007ffdb5d45a548731c694d9729bf2be
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 68ab0b5d1f
Original-Change-Id: I52ba2a3c1e0fffad7145eecd878aba8dc450ac0b
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18755
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454539
2017-03-14 07:25:22 -07:00
Lee Leahy
36c7266d41 UPSTREAM: soc/intel/common: Indent code with tabs
Fix the following error detected by checkpatch.pl:

ERROR: code indent should use tabs where possible

TEST=Build and run on Galileo Gen2

Change-Id: If26414313050f4e9a045cf64e0dd9b007b34d610
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 42e605be19
Original-Change-Id: I61c4f01216cb6c788cf6da988c414bbb9648d502
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18754
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454538
2017-03-14 07:25:21 -07:00
Jeffy Chen
cf18ed7b8f bob: tpm: cr50: add irq clear/irq status for tpm irq
BUG=b:35647967
TEST=boot from bob

Change-Id: I50c053ab7a6f6c14daee4fb2ab1cdcaeee2d67da
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/452286
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-03-14 00:40:06 -07:00
Jeffy Chen
223257d486 rockchip: gpio: add gpio_input_irq & gpio_irq_status
BUG=b:35647967
TEST=boot from bob

Change-Id: I055ad5f59285cee3110d1e7cb1a53a60144712e4
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/452285
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-03-14 00:40:05 -07:00
Jeffy Chen
abe212ffb0 tpm: spi: cr50: using tpm irq to sync tpm transaction
BUG=b:35647967
TEST=boot from bob

Change-Id: Ib64107b17fb6e93dbe626ce92f3bc9da8b84784e
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/452284
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-03-14 00:40:05 -07:00
Jeffy Chen
9407c1fbc0 tpm: spi: cr50: try to wake cr50 if it is asleep
BUG=b:35775002
TEST=boot from bob

Change-Id: I6324f3c02da55a8527f085ba463cbb1f4fb5dc2e
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/452283
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-03-13 22:40:02 -07:00
Patrick Georgi
eabb1c209e Drop --exclude statement from .checkpatch.conf
It's an option only available in coreboot's checkpatch fork at this
time. Reenable when upstream (ie. Linux) supports it and that version
was downstreamed into cros_sdk.

TEST=cros hooks don't fail on coreboot

Change-Id: I6e718ea13fda19df13a62295359f1607d122ef58
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/453778
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-03-13 17:53:59 -07:00
Lee Leahy
483b7db48b UPSTREAM: src/lib: Use tabs instead of spaces
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: code indent should use tabs where possible
ERROR: switch and case should be at the same indent
WARNING: Statements should start on a tabstop
WARNING: please, no spaces at the start of a line
WARNING: please, no space before tabs
WARNING: suspect code indent for conditional statements
WARNING: labels should not be indented

TEST=Build and run on Galileo Gen2

Change-Id: Id17a59b48fcb5ddce232eb63cf86e04f13278bdb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e20a3191f5
Original-Change-Id: Iebcff26ad41ab6eb0027b871a1c06f3b52dd207c
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18732
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/453377
2017-03-13 13:07:57 -07:00
Shobhit Srivastava
6dd5c87530 UPSTREAM: google/poppy: Enable internal pull-up on PWRBTN#
Enable an internal pull-up on the power button input as short
press is resulting in power button override being asserted.

BUG=b:36111214
BRANCH=none
TEST=tested on poppy board to ensure quick power button press does
not result in a shutdown due to power button override.

Change-Id: Ibaded11de936e563db0a4d83bcaec059549ab360
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cdd7686a9d
Original-Change-Id: I3a25b78562e2302b6f7575e64c87ae8142690701
Original-Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18734
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/453684
2017-03-13 05:16:04 -07:00
Lee Leahy
84012189ef UPSTREAM: src/lib: Remove space between function name and (
Fix the following warning detected by checkpatch.pl:

WARNING: space prohibited between function name and open parenthesis '('

TEST=Build and run on Galileo Gen2

Change-Id: If2402e10741ff3c64b4a487a5ecfc91887d1301a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 38768c328a
Original-Change-Id: I8f3c79302dc5eb1861ffb245617a27addf8653ef
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18731
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/453683
2017-03-13 05:16:04 -07:00
Lee Leahy
3c8b64c5c0 UPSTREAM: src/lib: Move trailing statements to next line
Fix the following error detected by checkpatch.pl:

ERROR: trailing statements should be on next line

The remaining error is a false positive in libgcov.c where the if
statement spans several lines with conditional compilation directives
intertwined.

TEST=Build and run on Galileo Gen2

Change-Id: I6aaa33ec9faa16195106e8bf1e778d6148870f23
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b6ee0f9d92
Original-Change-Id: I37fcef78e9323340bac1367ae1c5fde334f5ce10
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18730
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/453682
2017-03-13 05:16:03 -07:00
Lee Leahy
370c46c877 UPSTREAM: src/include: Remove braces for single statements
Fix the following warning detected by checkpatch.pl:

WARNING: braces {} are not necessary for single statement blocks

TEST=Build and run on Galileo Gen2

Change-Id: Ic05932eec8c057c0501915ed62478db487f20135
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bfdb8937b2
Original-Change-Id: I00b59f6a27c3acb393deaa763596363b7e958efd
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18654
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/453681
2017-03-13 05:16:03 -07:00
Lee Leahy
e4befad6d1 UPSTREAM: src/include: Open brace on same line as enum or struct
Fix the following errors and warning detected by checkpatch.pl:

ERROR: open brace '{' following enum go on the same line
ERROR: open brace '{' following struct go on the same line
ERROR: that open brace { should be on the previous line
WARNING: missing space after struct definition

TEST=Build and run on Galileo Gen2

Change-Id: Ieb89b152cebcf88cfde80b57bbaf9cf7130b8f04
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6625ecc344
Original-Change-Id: I856235d0cc3a3e59376df52561b17b872b3416b2
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18653
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/453680
2017-03-13 05:16:02 -07:00
Lee Leahy
e7ff5b5fa4 UPSTREAM: src/include: Remove spaces before tabs
Fix the following warning detected by checkpatch.pl:

WARNING: please, no space before tabs

TEST=Build and run on Galileo Gen2

Change-Id: Ib41ee378b8ad74a0171b12e1cee7f24b6aa20905
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 84d20d0eb3
Original-Change-Id: If60a58021d595289722d1d6064bea37b0b0bc039
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18652
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/453679
2017-03-13 05:16:02 -07:00
Lee Leahy
fe76d4aaa9 UPSTREAM: src/include: Remove spaces before ( and after )
Fix the following error messages found by checkpatch.pl:

ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'

TEST=Build and run on Galileo Gen2

Change-Id: I9d41c8298e84a8370767eb6d492802cf388c987e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91d1e76fd1
Original-Change-Id: I2a9a0df640c51ff3efa83dde852dd6ff37ac3c06
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18651
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/453678
2017-03-13 05:16:01 -07:00
Paul Menzel
547c7a7598 UPSTREAM: lenovo/t400/dock.c: Fix issues found by checkpatch.pl
BUG=none
BRANCH=none
TEST=none

Change-Id: I3663841b79ec0bfab4c8b442ff955ef415b60fd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4eb155cee4
Original-Change-Id: If7ebab8af1ae0c048cb89c2feb5f6a65848b6952
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18767
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/453438
2017-03-12 03:30:52 -07:00
Kyösti Mälkki
5841884eea UPSTREAM: lenovo/t400: Rewrite dock from t60
Old dock.c copied from x201 was incorrect. Do a rewrite of t60 dock
code as pnp devices.

Fixes USB and serial on the dock, if it is already connected when
computer is powered on. DVI and ethernet worked without this patch.

Hot-plug is yet to be fixed.

BUG=none
BRANCH=none
TEST=none

Change-Id: I7508874d9c821e31e2297ee5876a573b9eac990f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9ab5adbde4
Original-Change-Id: Ib20a0eff10d0cde92dd089baf4fca28b117dc999
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18054
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/453375
2017-03-11 17:04:39 -08:00
Lee Leahy
3f92295606 UPSTREAM: src/include: Add space after +
Fix the following error detected by checkpatch.pl:

ERROR: need consistent spacing around '+' (ctx:WxV)

Test: Build and run on Galileo Gen2

BUG=none
BRANCH=none
TEST=none

Change-Id: I7dd42e1dd06992896ea52664fc09859daa743bbf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f3d07f274e
Original-Change-Id: Idd5f2a6d8a3c8db9c1a127ed75cec589929832e3
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18650
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/453374
2017-03-11 17:04:39 -08:00
Lee Leahy
6794da3340 UPSTREAM: src/include: Add parenthesis around macros
Fix the following error found by checkpatch.pl:

ERROR: Macros with complex values should be enclosed in parentheses

False positives are detected for attribute macros.  An example is:

ERROR: Macros with complex values should be enclosed in parentheses
+#define BOOT_STATE_INIT_ATTR  __attribute__ ((used, section
(".bs_init")))

False positive also generated for macros for linker script files.  An
example is:

ERROR: Macros with complex values should be enclosed in parentheses
+#define CBFS_CACHE(addr, size) \
+       REGION(cbfs_cache, addr, size, 4) \
+       ALIAS_REGION(cbfs_cache, preram_cbfs_cache) \
+       ALIAS_REGION(cbfs_cache, postram_cbfs_cache)

False positives generated for assembly code macros.  An example is:

ERROR: Macros with complex values should be enclosed in parentheses
+#define DECLARE_OPTIONAL_REGION(name) asm (".weak _" #name ", _e" #name
)

False positive detected when macro includes multiple comma separated
values.  The following code is from src/include/device/azalia_device.h:

        (((codec) << 28) | (0x01720 << 8) | ((val) & 0xff)),    \
        (((codec) << 28) | (0x01721 << 8) | (((val) >> 8) & 0xff)), \
        (((codec) << 28) | (0x01722 << 8) | (((val) >> 16) & 0xff)), \
        (((codec) << 28) | (0x01723 << 8) | (((val) >> 24) & 0xff))

TEST=Build and run on Galileo Gen2

Change-Id: I55c349a221e79f80ce4e1659e3e473b4e04444b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f00e446e74
Original-Change-Id: I6e3b6950738e6906851a172ba3a22e3d5af1e35d
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18649
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/453373
2017-03-11 17:04:38 -08:00
Lee Leahy
c9b65eec06 UPSTREAM: src/include: Add space before (
Fix the following error detected by checkpatch.py:

ERROR: space required before the open parenthesis '('

TEST=Build and run on Galileo Gen2

Change-Id: Ia1e107546eb92ada8d1e495aa24166133bb03686
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 86f60a9c8f
Original-Change-Id: I6969e63f750f327afff1a0efa1aab56d477af0df
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18645
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/453372
2017-03-11 17:04:38 -08:00
Lee Leahy
a9856d835a UPSTREAM: commonlib: Remove space after *
Fix the following error detected by checkpatch.pl:

ERROR: "foo * bar" should be "foo *bar"

TEST=Build and run on Galileo Gen2

Change-Id: I0683d6cb63de58347b020ee40b5b6cb0e87cf2ef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 36d5b41e62
Original-Change-Id: If68dfa2b49c61d574f35192f94d1a6642069fa7f
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18752
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/453371
2017-03-11 17:04:37 -08:00
Lee Leahy
fba5bc3209 UPSTREAM: commonlib: Fix issues with { } and else
Fix the following errors and warning detected by checkpatch.pl:

ERROR: open brace '{' following struct go on the same line
ERROR: else should follow close brace '}'
WARNING: else is not generally useful after a break or return

False positives are detected for the following checkpatch.pl error.
ERROR: that open brace { should be on the previous line
These false positives are in cbfs.c for two function definitions.

TEST=Build and run Galileo Gen2

Change-Id: I5784e3d762f9d84582fce18239a04cb21d89eebf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 72c60a472b
Original-Change-Id: Ic679ff3a2e1cfc0ed52073c20165e05bf21d76f3
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18750
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/453370
2017-03-11 17:04:37 -08:00
Lee Leahy
1cd21171c6 UPSTREAM: commonlib: Wrap lines at 80 columns
Fix the following error detected by checkpatch.pl:

ERROR: code indent should use tabs where possible

TEST=Build and run on Galileo Gen2

Change-Id: I58ed33b3ef4e3fc6ada4fa17ac14c80e7cdcc1e3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f339973d6f
Original-Change-Id: I3a44a02d4cd1be6b2bb2f52fc832e673a580e562
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18749
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/453369
2017-03-11 17:04:36 -08:00
Lee Leahy
4f0977a850 UPSTREAM: commonlib: Fix spacing issues
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: space required after that ',' (ctx:VxV)
ERROR: space required after that ';' (ctx:VxV)
ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
WARNING: please, no spaces at the start of a line
WARNING: please, no space before tabs

TEST=Build and run on Galileo Gen2

Change-Id: Iddd4e67830cccf73bc064d84ee3f7a03737f1e29
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d5a2a292b0
Original-Change-Id: I54877f60eb5fdf3f6d8729711c55ff5a284d22cf
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18748
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/453368
2017-03-11 17:04:36 -08:00
Lee Leahy
137b9ae242 UPSTREAM: drivers/intel/fsp2_0: Switch from binary to decimal
Fix the following warning detected by checkpatch.pl:

WARNING: Avoid gcc v4.3+ binary constant extension:

TEST=Build and run on Galileo Gen2

Change-Id: Icf867673b99f74be331ab81a2b41313d2beaca61
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce46c5b6a1
Original-Change-Id: Ied50b94ecae4d3bde5812f6b54bbe2421fd48588
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18747
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/453367
2017-03-11 17:04:36 -08:00
Lee Leahy
205b3a6fb1 UPSTREAM: drivers/intel/fsp2_0: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:

WARNING: line over 80 characters

TEST=Build and run on Galileo Gen2

Change-Id: I2e29e1b9ca4dd35a3b269dd6b2be1d2161d58ef5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7732b35fb7
Original-Change-Id: I0e5acef53d558948b7713cfe608cd346ddc5e9fe
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18746
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/453366
2017-03-11 17:04:35 -08:00
Lee Leahy
ac3e815e96 UPSTREAM: drivers/intel/fsp2_0: Remove braces for single statements
Fix the following warning detected by checkpatch.pl:

WARNING: braces {} are not necessary for single statement blocks

TEST=Build and run on Galileo Gen2

Change-Id: I4f22414276b8e296fca20a2ba262e818ed004d0d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e686ee8bf7
Original-Change-Id: Ibd351703e60acebbacd6ae5b1a2fa1cb34fd3ff9
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18745
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/453365
2017-03-11 17:04:35 -08:00
Lee Leahy
5de927158e UPSTREAM: drivers/intel/fsp2_0: Fix spacing issues
Fix the following errors detected by checkpatch.pl:

ERROR: space prohibited before that close parenthesis ')'
ERROR: space required before the open parenthesis '('
ERROR: space prohibited before open square bracket '['
ERROR: spaces required around that ':' (ctx:VxE)

TEST=Build and run on Galileo Gen2

Change-Id: I1227c8970dcbba982e6e51b4028174343daa5988
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b2b97a5db2
Original-Change-Id: I085aaaa9e276c60eded6edf3be0325ed2402702a
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18744
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/453364
2017-03-11 17:04:34 -08:00
Lee Leahy
ceeb67af66 UPSTREAM: drivers/intel/fsp2_0: Add space before *
Fix the following error detected by checkpatch.pl:

ERROR: "(foo*)" should be "(foo *)"

False positives are generated by checkpatch for the following condition
which is not properly detecting the variable type:
ERROR: need consistent spacing around '*' (ctx:WxV)
The false positives are found in debug.h and upd_display.c

TEST=Build and run on Galileo Gen2

Change-Id: Ia1a03a6f4df599f8742790d558d400668a8d8fca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27de768112
Original-Change-Id: I0e871d64544ebf5eacbae46466cf7aefbfa701eb
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18743
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/453363
2017-03-11 17:04:34 -08:00
Lee Leahy
f96a2cd575 UPSTREAM: drivers/intel/fsp2_0: Use tabs for indent
Fix the following warning detected by checkpatch.pl:

WARNING: please, no spaces at the start of a line

TEST=Build and run on Galileo Gen2

Change-Id: I1c318762b99d0a14520c2caa0e5a4a4cce28dd81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 30bdb52e4c
Original-Change-Id: I7cb35c8b5d7ff97849e666ce7f75d4e4763bb2a7
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18742
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/453362
2017-03-11 17:04:33 -08:00
Barnali Sarkar
4d4655f184 UPSTREAM: soc/intel/common: Pass the minimum possible string length for strncpy
In strncpy() function of dimm_info_fill(), the minimum possible size
of Module Part Number of DIMM is passed as argument.

BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS Table from Kernel command "dmidecode".

Change-Id: Id26d55a11f8c4bcbdedc6c34d7b48198e2501f4f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6497cd9744
Original-Change-Id: Icc7667149eae9705b91e271628af1b443eb8556e
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18617
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/453361
2017-03-11 17:04:33 -08:00
Katherine Hsieh
87e0803e7c UPSTREAM: google/sand: Add devicetree.cb file for sand
It is a copy from baseboard/devicetree.cb  (coreboot.org ToT)

BUG=b:35775065
BRANCH=reef
TEST=emerge-sand coreboot

Change-Id: I22012641146da6e15f66343bcd87f7e25d3a5be8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 674c089922
Original-Change-Id: I5ba86e54ccfbf5af7bf0e9ad8fe7bf22020e48ee
Original-Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18703
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/453360
2017-03-11 17:04:32 -08:00
Tim Chen
da4b682862 UPSTREAM: mainboard/google/reef: Modify TCPU, TSR2 and TRT table
Update the DPTF parameters based on thermal test result.
(ZHT_DPTF_EVT2_v0.5_20170306.xlsx)

1. Update DPTF TCPU critical trigger point.
   TCPU critical point: 105

2. Update DPTF TSR2 passive trigger point.
   TSR2 passive point: 58

3. Change thermal relationship table (TRT) setting.
   Change CPU Throttle Effect on CPU sample rate to 10secs.
   Change Charger Effect on Temp Sensor 2 sample rate to 30secs.
   Change CPU Effect on Temp Sensor 2 sample rate to 60secs.

BUG=b:35583586
BRANCH=master
TEST=build and boot on electro dut

Change-Id: Iee24773e9c6d078cf6e41d807aa6566f79608b1c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 327c5c60dd
Original-Change-Id: I85564ccdaf327eeaa13bf1f31d9a933609a21582
Original-Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18610
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/453359
2017-03-11 17:04:32 -08:00
Nico Huber
0a8947fe29 UPSTREAM: soc/intel/broadwell: Rework IGD's CDClk selection
CDClk selection was wrong in some corner cases (e.g. ULX SKUs) and,
for Broadwell, never took the devicetree config into account.

Rewrite the selection with the following in mind:

  o cpu_is_ult() might return `true` for ULX SKUs, too,

  o ULX and Broadwell-ULT SKUs can be `overclocked` with additional
    cooling, so leave that as devicetree option.

For Haswell, the following frequency selections are valid:

  o ULX: 337.5MHz by default, 450MHz optional
  o ULT: 450MHz only (maybe 337.5MHz too, documentation varies,
                      it wasn't selectable before either)
  o others: 540MHz by default, 450MHz optional

For Broadwell:

  o ULX: 450MHz by default, 337.5MHz / 540MHz optional
  o ULT: 540MHz by default, 337.5MHz / 450MHz / 675MHz optional
  o others: 667MHz by default, 337.5MHz / 450MHz / 540MHz optional

Side effects: A too high setting in the devicetree results in the
highest possible frequency now, Haswell non-ULT/ULX defaults to 540MHz
instead of 450MHz.

BUG=none
BRANCH=none
TEST=none

Change-Id: I2539a6b66b677217a2c5e44c4fe2fc7b8b5624bc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e392f414cd
Original-Change-Id: Iec12752f2a47bf4a5ae6077c75790eae9378c1b2
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/17768
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/453358
2017-03-11 17:04:31 -08:00
Julius Werner
c2781eeef5 oak: Configure SD card detect pin with a pull-up
SD card detect pins should normally have a pull-up. It seems that for
micro-SD cards this doesn't really matter all that much, but for the
full-size slots we have on some Oak-derivatives (like Hana) it does.

BRANCH=oak
BUG=b:35854317
TEST=Booted Hana, confirmed that card detect no longer seemed stuck-on.
Booted Elm and confirmed that SD card behavior didn't change.

Change-Id: I428ac92efb07f94265673b04e0e0dd452649b9fd
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452861
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
2017-03-10 19:52:30 -08:00
Xing Zheng
f34d254e1d rockchip/rk3399: soc: resize reserve memory
Reserve the whole TZRAM area because it will be marked as secure-only
by BL31 and can not be accessed by the non-secure kernel.

CQ-DEPEND=CL:452659
BUG=chrome-os-partner:57361
BRANCH=firmware-gru-8785.B
TEST=the reserve memory is resized

Change-Id: I39c4cb530f41a7b0f7f3064125072dd85b62276f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/418102
Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit ea9fe064a9b1e1ce81fca74f829a0fb6e78ce426)
Reviewed-on: https://chromium-review.googlesource.com/452640
Tested-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
2017-03-11 00:36:31 +00:00
Hannah Williams
af7ab61fc1 UPSTREAM: ifdtool: Add SPI_FREQUENCY_50MHZ_30MHZ as a valid freq
Without this change, error "Unknown descriptor version: 4" will be
returned if this frequency is selected (seen on GLKRVP)

BUG=none
BRANCH=none
TEST=none

Change-Id: Ic95473e14f12298827297abc17e066d3a9f35783
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 589fc3473e
Original-Change-Id: Ib5bfb996b85c7245d8f9c70988bfd5bbac882d74
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18688
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452897
2017-03-10 10:54:49 -08:00
sowmyav
4cdbd0d9fa UPSTREAM: soc/intel/skylake:Add _DSM method to reduce D3 cold delay for eMMC controller
eMMC Controller is taking over 100ms to resume during runtime which
results in I/O latency issues on the Skylake systems like Cave and Caroline.

This patch adds _DSM method for eMMC comtroller for specifying the
device readiness durations. Function index 9 returns package of five
integers to set D3 cold delay to zero and ACPI constant Ones for the
elements where overriding the default values is not desired.

BUG=b:35774937
BRANCH=none
TEST=update caroline coreboot and test i/o latency is under 100ms

Change-Id: I7ebb13c7f72279c9c1727f68e0ad96949715bf9a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d448a5e98b
Original-Change-Id: Iacc8aa8560897da8770fe559ca8cd17aaf6ebeba
Original-Signed-off-by: Sowmya V <v.sowmya@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18532
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452896
2017-03-10 10:54:48 -08:00
Patrick Rudolph
8d120a532b UPSTREAM: device/dram/ddr2: Add common ddr2 spd decoder
Decode DDR2 SPD similar to DDR3 SPD decoder to ease
readability, reduce code complexity and reduce size of
maintainable code.

Rename dimm_is_registered to spd_dimm_is_registered_ddr3 to avoid
compilation errors.

BUG=none
BRANCH=none
TEST=none

Change-Id: I2580a164627a0348da02aad6dbbe5311c442fe35
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6e53ae6f5c
Original-Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18273
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452895
2017-03-10 10:54:48 -08:00
Venkateswarlu Vinjamuri
cbfcec9e1b UPSTREAM: mainboard/google/reef: Configure SDCARD card detect pin
This configures GPIO_177 as an input pin for SDCARD card
detect. This also changes the ownership of the pin from ACPI
to GPIO driver.

Assign the sdcard card detect pin in devicetree for reef variants.

CQ-DEPEND=CL:448173
BUG=chrome-os-partner:63070
TEST=None

Change-Id: I6a146d62c0e7f6715d5b63180bfe8cd7f85dd56e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e4d12c5b1
Original-Change-Id: Ia8aef60bd7d0ea36afb39f76fab051aa46a2ed64
Original-Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18497
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452894
2017-03-10 10:54:48 -08:00
Venkateswarlu Vinjamuri
ad9871dd5c UPSTREAM: soc/intel/apollolake: Add PM methods to power gate SD card
This implements dynamic generation of sdcard GpioInt in SSDT.
GpioInt in SSDT generation is based on the card detect GPIO if
it is provided by the mainboard in devicetree.

This implements GNVS variable to store the address of sdcard cd pin.
GNVS used to store rxstate of the sdcard cd pin to get card presence.

Add _PS0/_PS3 methods to power gate the sd card controller in
S0ix and runtime PM.

CQ-DEPEND=CL:448173
BUG=chrome-os-partner:63070
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should enter S0ix and resume with no issue.

Change-Id: I13a4250606be8adb7a180b4ec3f58e89f197101b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6dd7b402d5
Original-Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87
Original-Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18496
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/452893
2017-03-10 10:54:47 -08:00
Paul Menzel
0e6f3b862c UPSTREAM: asus/m2v: Make _CRS methods serialized
Address the iasl 20160108-64 (Ubuntu 16.04) warnings below.

```
Intel ACPI Component Architecture
ASL+ Optimizing Compiler version 20160108-64
Copyright (c) 2000 - 2016 Intel Corporation

dsdt.aml    245:      Method (_CRS, 0, NotSerialized)
Remark   2120 -                 ^ Control Method should be made Serialized (due to creation of named objects within)

dsdt.aml    262:      Method (_CRS, 0, NotSerialized)
Remark   2120 -                 ^ Control Method should be made Serialized (due to creation of named objects within)

dsdt.aml    277:      Method (_CRS, 0, NotSerialized)
Remark   2120 -                 ^ Control Method should be made Serialized (due to creation of named objects within)

dsdt.aml    295:    Method(_CRS, 0) {
Remark   2120 -              ^ Control Method should be made Serialized (due to creation of named objects within)
```

BUG=none
BRANCH=none
TEST=none

Change-Id: Ic33a018d9dc9b9acec079499684401da17177681
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d4f92fa603
Original-Change-Id: Id5b0f33fba8ea25e4a6aa4f01c69a69aaf5aef23
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18323
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452892
2017-03-10 10:54:47 -08:00
Paul Menzel
5b601e0fac UPSTREAM: cpu/amd/agesa: Unify init files
The init files for the AMD families using the AGESA platform
initialization code are quite similar. So reduce the differences, by
using the same comments, variable names, console messages, and blank
lines.

BUG=none
BRANCH=none
TEST=none

Change-Id: I290453cd875ed445755de6218f9349bc9906e481
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 22f32c723c
Original-Change-Id: Id4a3a5c3812a34627d726cdcbe8f4781a14be724
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18507
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/452891
2017-03-10 10:54:46 -08:00
Alexander Couzens
4fdc6148a9 UPSTREAM: .gitignore: ignore *.swo and option *.roms
BUG=none
BRANCH=none
TEST=none

Change-Id: Id32822a7100d5a88baa9d3c5b14f218e02f69463
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dd6f75ae6e
Original-Change-Id: I7403f548bae918ca813a9295bfb095a7c4c51e21
Original-Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Original-Reviewed-on: https://review.coreboot.org/15220
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452890
2017-03-10 10:54:46 -08:00
Paul Menzel
bf315a45d2 UPSTREAM: northbridge/intel/i440bx: Align code
BUG=none
BRANCH=none
TEST=none

Change-Id: I483868170597138f3cb3b2df9684cecb8d8f7163
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7c414e78cc
Original-Change-Id: Idd4127f7491524121b4b65c6fb9511e2c8159912
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18609
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452889
2017-03-10 10:54:45 -08:00