Implement functions to write the AML bytes corresponding to
CreateBitField for both OP buffers and named buffers.
TEST=Calling 'acpigen_write_create_buffer_bit_field' results in the AML
code sequence being written which decompiles to ASL as expected.
Change-Id: Ia5c06c2e8564b64de386871b2faf79c433e5a1da
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86630
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement functions to write the AML bytes corresponding to
'If (LNotEqual (...))' which is equivalent to 'If (LNot (LEqual (...)))'
for the value types combinations 2 OPs, OP and value, and namestring and
value.
TEST=Calling 'acpigen_write_if_lnotequal_op_int' results in the AML code
sequence being written which decompiles to ASL as expected.
Change-Id: I6c664bc4d30a49ae990eeb9f0e0776cac37efc57
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit introduces the `HAVE_EARLY_POWEROFF_SUPPORT` Kconfig option
and the `platform_do_early_poweroff()` API.
The Kconfig option enables platform-specific early power off support,
which is often required on Intel platforms. The corresponding API allows
platforms to implement the necessary hardware operations for early power
off, typically before memory initialization.
BUG=b:339673254
TEST=Able to build and boot google/brox.
Change-Id: I05b9882e100825a4fb733163a65f820c8c943361
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86417
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a new UX locale message to display a warning when the
battery is critically low.
The message informs the user about the low battery and indicates that
the system is shutting down.
This change ensures that users are notified before the system
unexpectedly shuts down due to low battery.
BUG=b:339673254
TEST=Built and booted google/brox.
Change-Id: I75c7a0d4d439901098c7f17a1dc90355307116ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch refactors the `ux_locales_get_text` API to handle fallback
text (English) internally, rather than relying on the caller. It
introduces message IDs for lookups, enabling the API to locate both
the UX locale name and fallback text based on the ID.
With this patch, `ux_locales_get_text` API locates UX locales message
based on message ID.
`ux_locales_get_text` retrieves fallback text message depending
upon the message ID if UX locales is not available.
This centralizes fallback handling and simplifies adding future
messages without per-SoC duplication.
BUG=b:339673254
TEST=Built and booted google/brox. Verified eSOL display.
Change-Id: I4952802396265b9ee8d164d6e43a7f2b3599d6c0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit adds the Panther Lake Intel Dynamic Tuning
Technology (Intel DTT) PCI Device ID to the list of supported devices
in the ACPI Common Block DTT driver.
The Panther Lake Intel DTT PCI ID is defined in document #815002,
"Panther Lake U/H Processor - External Design Specification - Volume
1".
TEST=The SSDT ACPI table includes the DPTF device definition on
fatcat board.
Change-Id: Ia8dbe86efdf341a629de037d37750b79395ec3e8
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
This change fixes CRC calculations in cases where an expression
calculating the address using pointer arithmetic is passed into the
macro.
Change-Id: I55bbd2f208a94068ea3b3b3ae97b1683434c3007
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86099
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some keyboard controllers need to have a specific bit in the command
byte set (e.g. PC_KBC_TRANSLATE) in order for the keyboard to function
properly.
Change-Id: I8745d1848f223634043eecc4659021a76a2b239b
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85330
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The fw_cfg device can be used by other qemu boards outside i440fx (and
q35, which manually includes the code). Factor out the fw_cfg code as a
separate driver that qemu mainboards can enable.
Change-Id: I8c5c4cb5f5478abd21aab8e8d0b503db41d81d40
Signed-off-by: Carlos López <carlos.lopez@openchip.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85673
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds device id for Crashlog and Telemetry. CPU crashlog
record is stored in punit SRAM.
Source: EDS 815002
BUG=None
TEST=Build fatcat and boot with Panther Lake SoC with added
device id.
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Change-Id: I2959623986108a2c5e3dce16e892913a42d71755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Add a new option backend that uses values stored in CBFS files, similar
to the SeaBIOS runtime config options stored in files with the etc/
prefix. Options should be stored in CBFS with the option/ prefix. Values
can be set using `cbfstool coreboot.rom add-int -n option/<option-name>
-i <value>`. For simplicity, options should be stored in the COREBOOT
(RO) FMAP region, which is the default for cbfstool. This backend is not
available in SMM due to CBFS dependencies on vboot functions which are
not added to SMM, and thus the fallback will be returned by calls to
get_uint_option() in SMM.
Tested with QEMU Q35 by setting various options for "sata_mode" and
observing the console output for the SATA controller mode during
i82801ix_sata initialization.
Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This resolves a crash issue observed on Meteor Lake and introduced by
commit 70bdd2e1fa ("cpu/x86/topology:
Simplify CPU topology initialization"). This commit simplifies the
code and provides more detailed CPU topology information by
generalizing the use of the Extended Topology Enumeration Leaves
0x1f. As a result, the coreboot APIC core_id field does not provide
the fully detailed path information.
It turns out that the topology core identifier is used by the coreboot
MP service mp_get_processor_info() implementation. But the MP Service
EFI_CPU_PHYSICAL_LOCATION data structure only captures information
about the package, core, and thread. The core identifier returned to
the MP service caller must incorporate the full hierarchical path (die
group, die, module, tile, module and core).
This commit adds a new field to the cpu topology structure to
represent the core ID within the package.
For reference, here is that signature of the crash:
LAPIC 0x40 in X2APIC mode.
CPU Index 2 - APIC 64 Unexpected Exception:13 @ 10:69f3d1e4 - Halting
Code: 0 eflags: 00010046 cr2: 00000000
eax: 00000001 ebx: 69f313e8 ecx: 0000004e edx: 00000000
edi: 69f38018 esi: 00000029 ebp: 69aeee0c esp: 69aeedc0
[...]
The crash occurred when FSP attempted to lock the Protected
Processor Inventory Number Enable Control MSR (IA32_PPIN_CTL
0x4e).
69f3d1d3: 8b 43 f4 mov -0xc(%ebx),%eax
69f3d1d6: 89 4d c4 mov %ecx,-0x3c(%ebp)
69f3d1d9: 89 45 dc mov %eax,-0x24(%ebp)
69f3d1dc: 8b 55 c4 mov -0x3c(%ebp),%edx
69f3d1df: 8b 45 c0 mov -0x40(%ebp),%eax
69f3d1e2: 8b 4d dc mov -0x24(%ebp),%ecx
69f3d1e5: 0f 30 wrmsr
69f3d1e7: e9 ee fd ff ff jmp 0xfffffe39
FSP experiences issues due to attempting to lock the same register
multiple times for a single core. This is caused by an inconsistency
in the processor information data structure, where multiple cores
share the same identifier. This is not permitted and triggers a
General Protection Fault Exception.
TEST=Executing CpuFeaturesPei.efi in FSP-S does not crash on a rex
board.
Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86004
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
This commit introduces the missing PCI device IDs for Panther Lake
CNVi Bluetooth devices. These IDs are listed in document #815002 -
Panther Lake U/H Processor - External Design Specification Volume 1.
TEST=The CNVB device is now present in the ACPI SSDT table when the
cnvi_bluetooth device is enabled.
Change-Id: I45b42b0694d530763d4cd321aefc64141d088e2b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85959
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a module_id field to the cpu_topology structure.
This field is used to identify the module that a CPU is located
on. This information is useful for power management and other
purposes.
Change-Id: I1c8a76dce48c0539a3f36015674553a2461dec27
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85577
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit renames the Meteor lake Touch Controller device IDs to
include the supported bus/protocol for clarity. The IDs comes from
document #640228 - Meteor Lake External Design Specification volume 1.
Change-Id: I60d9bec60d0578bd5a12a4df25248b7ae58539d6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85644
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a mechanism so that coreboot can provide a list of options to
post-coreboot code. The options are grouped together into forms and
have a meaning name and optional help text. This can be used to let
payloads know which options should be displayed in a setup menu,
for instance. Although this system was written to be used with edk2,
it has been designed with flexibility in mind so that other payloads
can also make use of this mechanism. The system currently lacks a way
to describe where to find option values.
This information is stored in a set of data structures specifically
created for this purpose. This format is known as CFR, which means
"coreboot forms representation" or "cursed forms representation".
Although the "forms representation" is borrowed from UEFI, CFR can
be used in non-UEFI scenarios as well.
The data structures are implemented as an extension of cbtables records
to support nesting. It should not break backwards compatibility because
the CFR root record (LB_TAG_CFR_ROOT) size includes all of its children
records. The concept of record nesting is borrowed from the records for
CMOS options. It is not possible to reuse the CMOS records because they
are too closely coupled with CMOS options; using these structures would
needlessly restrict more capable backends to what can be done with CMOS
options, which is undesired.
Because CFR supports variable-length components, directly transforming
options into CFR structures is not a trivial process. Furthermore, CFR
structures need to be written in one go. Because of this, abstractions
exist to generate CFR structures from a set of "setup menu" structures
that are coreboot-specific and could be integrated with the devicetree
at some point. Note that `struct sm_object` is a tagged union. This is
used to have lists of options in an array, as building linked lists of
options at runtime is extremely impractical because options would have
to be added at the end of the linked list to maintain option order. To
avoid mistakes defining `struct sm_object` values, helper macros exist
for supported option types. The macros also provide some type checking
as they initialise specific union members.
It should be possible to extend CFR support for more sophisticated
options like fan curve points. Feedback about this is highly
appreciated.
Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74121
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to document 559910 Intel Connectivity Platforms BIOS
Guideline revision 8.2 and 9.2 specifications, both revision 0 and 1
are supported and share the same structure.
BUG=b:346600091
Change-Id: Id0e05a9db48445b9254701d2a09c19bfbd477284
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85586
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit rewrites the CPU topology initialization code to simplify
it and make it more maintainable.
The previous code used a complex set of if-else statements to
initialize the CPU topology based on the CPUID leaves that were
supported. This has been replaced with a simpler and more readable
function that follows the Intel Software Developer Manual
recommendation by prioritizing CPUID EAX=0x1f over CPUID EAX=0xb if
available.
The new code removes the need for separate functions to handle the
topology initialization for different CPUID leaves. It uses a static
array of bitfield descriptors to store the APIC ID descriptor
information for each level of the CPU topology. This simplifies the
code and makes it easier to add new levels of topology in the future.
The code populates the node ID based on the package ID, eliminating
the need for an extra function call.
Change-Id: Ie9424559f895af69e79c36b919e80af803861148
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85576
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
In order to debug stack smashing add a write breakpoint to the
stack canary (at _stack or _car_stack) and print the IP when the
stack canary is written.
TEST: Wrote to address _stack in ramstage and got the EIP of the
code that smashed the stack canary.
Change-Id: I8adf07a8425856795a4a71da5c41bec2244b02a8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The following functions are added:
_create_buffer_field
acpigen_write_create_buffer_byte_field
acpigen_write_create_buffer_word_field
acpigen_write_create_buffer_dword_field
acpigen_write_create_buffer_qword_field
These functions are to generate:
CreateByteField (<namestring> , offset, <field name>)
CreateWordField (<namestring> , offset, <field name>)
CreateDWordField (<namestring> , offset, <field name>)
CreateQWordField (<namestring> , offset, <field name>)
NOTE:
There are set of acpigen_write_create_[byte/word/dword/qword]_field
functions already, but the field can only be created from Arg[n] or
Local[n] variable objects. A Name object must be first assigned to such
variable. The new functions here will allow us to create field directly
from Name object.
BUG=none
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I725f17329c501c80d42034e0f6a2fccb2cef5915
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85197
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On platforms with multiple IOAPICs the GSI base must not be
linear, which is currently assumed by acpi_create_madt_ioapic_from_hw().
Integrate the existing struct device DEVICE_PATH_IOAPIC type and allow
to assign custom GSI bases for each IOAPIC. Write out the IOAPIC devices
into the MADT table if any.
For now, since no platform adds IOAPIC devices, the existing behaviour
remains the same. Allows to get rid of soc_get_ioapic_info().
Change-Id: Ie13d4f5c4f0704f0935974f90e5b7cf24e94aab3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add functions to send the RPMC-related commands to a RPMC-capable SPI
flash to provision the root key, update the HMAC key, increment the
monotonic counter, and request the monotonic counter data. To talk to
the flash chip, the command bytes and polling mechanism described in the
SFDP data structure of the flash are used.
The JESD260 specification was used as a reference.
Some of inspiration was taken from
github.com/teslamotors/coreboot/tree/tesla-4.12-amd
TEST=When used with the later patch that calls some of the functions
added in this patch, sending the RPMC increment monotonic counter
command to the RPMC-capable SPI flash, in this case W74M12JW, is
successful.
Change-Id: Ia9bd69d0105c66bf5ecb6c90e8c782a81912bd40
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84837
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These header files do not seem to be used in coreboot. Presumably
they're left over after the code that used them was removed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ide70239c7c2e93fff548d989735450396308c62b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85370
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Drive Strength BRI Rsp Object provides information from the OEM
platforms if they have replaced the Bluetooth Radio Interface resistor
to overcome the potential STEP errors on their designs. Based on
configuration, CNV firmware shall adjust the BRI Rsp line drive
strength.
The bri_resistor_value is encoded as follow:
| Bit | Val | Description | Default |
|------+-----+---------------------------------------------+---------|
| 0 | 0 | Device FW default values | 1 |
| | 1 | Override device FW default values | |
| 3:1 | 0 | Reserved (shall be set to 0) | 0 |
| 7:4 | 0 | DSBR override values (only if bit 0 is set) | 0xf |
| 31:7 | 0 | Reserved (shall be set to 0) | 0 |
Possible values:
- 0xf1 (default): indicates that the resistor on board is 33 Ohm
- 0x0 or 0xb1: indicates that the resistor on board is 10 Ohm
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=DSBR methods are added to the wifi device and bluetooth companion
device and they return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e300
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85017
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This feature provides ability to provide Wi-Fi PHY filter
Configuration. A well-defined dedicated filter on particular platform
can be used to perform the maximum Wi-Fi performance.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=WPFC method is added to the wifi device and return the data
supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e270
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84948
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extended Bluetooth Regulatory Descriptor (EBRD) SAR/RFE are safety
regulations for limiting antenna radiation near human contact. EBRD
provides option to provide up to three sets of TX power limits and
power restrictions.
As the EBRD table is related to the revision 2 of the BRDS, this
commit also adds support for this new revision.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=EBRD method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e250
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84947
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This feature provides ability to set the Bluetooth Dual Mac Mode
setting.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BDMM method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e240
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84946
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This feature provides ability to set the Bluetooth Ultra High
Band (UHB) settings per country. The bluetooth UHB country selection
is defined as follow (default is 0):
| Bit | Value | |
|-------+-------+---------------------------------------------------|
| 0 | 0 | No override; use BT device settings |
| | 1 | Force disable BT in all countries that are not |
| | | defined in the following bits |
| 1 | 0 | USA 6GHz BT disable |
| | 1 | 6GHz BT allowed in the USA (enabled only if the |
| | | device is certified to the USA) |
| 2 | 0 | Rest of the World 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Rest of the World (enabled |
| | | only if the device is certified to the rest |
| | | of the world) |
| 3 | 0 | EU countries 6GHz BT disable |
| | 1 | 6GHz BT allowed in the EU countries (enabled only |
| | | if the device is certified to the EU countries) |
| 4 | 0 | South Korea 6GHz BT disable |
| | 1 | 6GHz BT allowed in the South Korea (enabled only |
| | | if the device is certified to the South Korea) |
| 5 | 0 | Brazil 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Brazil (enabled only if |
| | | the device is certified to the Brazil) |
| 6 | 0 | Chile 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Chile (enabled only if the |
| | | device is certified to the Chile) |
| 7 | 0 | Japan 6GHz BT disable |
| | 1 | 6GHz BT allowed in Japan (enabled only if the |
| | | device is certified to Japan) |
| 8 | 0 | Canada 6GHz BT disable |
| | 1 | 6GHz BT allowed in Canada (enabled only if the |
| | | device is certified to Canada) |
| 9 | 0 | Morocco 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Morocco (enabled only if |
| | | the device is certified to the Morocco) |
| 10 | 0 | Mongolia 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Mongolia (enabled only if |
| | | the device is certified to the Mongolia) |
| 11 | 0 | Malaysia 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Malaysia (enabled only if |
| | | the device is certified to the Malaysia) |
| 31:12 | 0 | Reserved Should set to zeros |
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BUCS method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e231
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This feature provides ability to provide dual chain setting.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BDCM method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e220
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84943
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This feature provides ability to identify non-LTE platform and disable
BiQuad Bypass filter logic in hardware for Bluetooth usecases reducing
device power consumption.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BBFB method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e213
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The ACPI BPAG method provide information to controls the antenna gain
method to be used per country.
The antenna gain mode is a bit field (0 - disabled, 1 -enabled)
defined as follow:
- Bit 0 - Antenna gain in EU
- Bit 1 - Antenna gain in China Mainland
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BPAG method is added to the bluetooth companion device and return
the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e210
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add const qualifier for input of dev_is_active_bridge so that
dev_is_active_bridge could be used for both struct device * input
and const struct device * input.
TESTED=Build and boot on intel/avenuecity CRB
Change-Id: Ia4231534c87cd13d4e6e4d606733f9eb11221ac1
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Add a helper function to identify PCI IOAPICs.
Will be used in the following commits.
Change-Id: Ibe50934260b025575440fd52eace73fe2327a193
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
PRMRR (Protected Region Memory Range Region) are not accessible as
normal DRAM regions and needs to be explicitly reserved in memory
map.
Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Definitions of __fls/__ffs from lib.h and fms/fls from
cpu/x86/mtrr.h are duplicated. Use definition from lib.h which is
more generic.
Change-Id: Ic9c6f1027447b04627d7f21d777cbea142588093
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Suggested-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85104
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fill 'rpmc_caps' struct inside the 'spi_flash' struct with the RPMC info
from the SFDP table.
TEST=On a board with a W74M12JW SPI flash chip, the 'rpmc_caps' struct
has the expected entries (RPMC available, OP2 extended status as polling
method, 4 RPMC counters, OP1 is 0x9b, and OP2 is 0x96).
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a8332bffe93e1691f6fc87c3936025f158f3ab9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Add basic support for the Serial Flash Discoverable Parameters (SFDP)
standard which can be used to discover the parameters to interact with
any SPI flash chip that supports this mechanism. This commit adds
functionality to find specific SFDP parameter headers and print all SFDP
parameter headers, but not to parse any SFDP parameter table. This is a
preparation for a follow-up patch that adds support to parse the RPMC
SFDP parameter table. Since 'find_sfdp_parameter_header' is only used in
the next patch, it's marked as static inline in this commit so that the
code still build; the 'inline' keyword will be removed again in that
follow-up patch.
For now, only the legacy access protocol using single bit SPI transfers
is supported, but this should cover most of the SPI NOR flash chips. In
any other case, the code will error out. It's also assumed that the SFDP
data blocks read from the SPI flash chip are small enough to fit into
the SPI host controller buffer and don't need to be broken up into
multiple transfers. This limitation will be addressed in a follow-up
patch.
JESD216F.02 was used as a reference.
TEST=On a board with a W74M12JW SPI flash chip, calling
'spi_flash_print_sfdp_headers' prints this on the console output:
Manufacturer: ef
SF: Detected ef 6018 with sector size 0x1000, total 0x1000000
SF: Exiting 4-byte addressing mode
SFDP header found in SPI flash.
major rev 0x1, minor rev 0x6, access protocol 0xff, number of headers 3
SFPD header with index 0:
table ID 0xff00, major rev 0x1, minor rev 0x6
table pointer 0x80, table length DWORDS 0x10
SFPD header with index 1:
table ID 0xff84, major rev 0x1, minor rev 0x0
table pointer 0xd0, table length DWORDS 0x2
SFPD header with index 2:
table ID 0xff03, major rev 0x1, minor rev 0x0
table pointer 0xf0, table length DWORDS 0x2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
As per commit 8651731537 ("sconfig: Move config_of_soc from device.h
to static.h") and commit 05a13e7ed9 ("sconfig: Move (WEAK_)DEV_PTR
from device.h to static.h"), sources that require access to the
devicetree should directly include static.h. This allows static.h to be
removed from device.h, eliminating many unnecessary dependencies on the
devicetree for objects that only need the device types and function
declarations.
Now that static.h has been included throughout the tree where necessary,
it can be removed from device.h.
Change-Id: Ie72840c71ffca2ada82456dda6a2c813f6a6c3ad
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84590
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Similar to commit 8651731537 ("sconfig: Move config_of_soc from
device.h to static.h"), move these macros to static.h to separate
dependencies on device.h and static.h. These macros resolve to device
alises that are declared in the generated static_devices.h header, so
move them to static.h which includes static_devices.h.
Since static.h remains included in device.h, any source that uses these
macros should still compile correctly. Subsequent commits will add
static.h to files that need them, after which static.h can be dropped
from device.h.
Change-Id: I1c76ad749769591da9c102b11eb618e93b68bd7c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84676
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
By default, PCH SMBus codes will be called to retrieve SPD data. This
patch adds a SPD IO layer so that SoC could implement its specific SPD
IO layer functions such as using Integrated Memory Controller to get
SPD data.
Change-Id: I656298aeda409fca3c85266b5b8727fac9bfc917
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84201
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds new DID0 PCI device IDs for Intel PTL-H.
Additionally, updates the System Agent driver's `systemagent_ids`
list and Panther Lake SoC bootblock to support these new IDs.
Source: Intel PTL-FAS. Document Number 812562
BUG=b:347669091
TEST=Build fatcat and boot with Panther Lake SoC with newly added
MCH ID.
With patch, coreboot log:
`[DEBUG] MCH: device id b004 (rev 00) is Pantherlake H`
`[DEBUG] MCH: device id b00a (rev 00) is Pantherlake H`
Change-Id: I56e795696f661d88828d7549f856eee19c46c942
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84916
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Add a helper method to read the PME capability.
Will be used in the following commit.
Change-Id: Id1fdc98c9ce86d3ddf8056bb609afc58008cf2e9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84793
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add and use a new helper function to determine if a device is
1) a PCIe device
2) it's mark hot-plug capable
Change-Id: I61cc013844024b43808cd2f054310cb6676ba69e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
