The darp10 has a second fan but no dGPU. The NFAN Method must exist, so
use the default hwmon names of "fan1" and "fan2" for labels.
Change-Id: I553deefea374b9dd916be6611850fca61afd490d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Add UCSI port data/port location data which is required for Windows to
use UCSI.
Adjustments taken from EC ACPI on Dell 5400/7410 Windows devices.
TEST=build/boot google/drallion, verify type-C ports functional under
Windows 11.
Change-Id: I04aa87ec10f320d1740cd3897864d154f2aea507
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87489
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Only run _REG on attach
- Reinitialize on WAK to support S3 / Hibernate
Adjustments taken from EC ACPI on Dell 5400/7410 Windows devices.
TEST=build/boot google/drallion, verify S3 sleep works properly as
well as S0ix.
Change-Id: I162d02c7d3c81f1106ddc65a3804f7112dda66b2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87488
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use a static variable to cache the board ID. It optimizes boot time by
reading the ID once per stage and retaining it for subsequent use.
Rewrite the function to avoid the unnecessary ChromeEC wrapper function.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I166ca1abdf7838f91319d0bcf11354055ed93eef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87247
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some ITE ECs take long time (15-20s) to complete flash erase operation
during EC software sync. Increasing the timeout value to 30s avoids
EC_CMD_FLASH_ERASE command from timing out. As this is just a timeout
value, it should not have any effect on the boot time.
BUGS=b:386920751, b:412210635
TEST= Verify that the EC_CMD_FLASH_ERASE(0x13) is not timing out while
performing EC sync. Below error is avoided,
```
[ERROR] Timeout waiting for EC process command 19!
[INFO ] VB2:update_ec() vb2ex_ec_update_image(select) returned 0x10000001
[INFO ] VB2:vb2api_fail() Need recovery, reason: 0x26 / 0x1
[INFO ] VB2:sync_ec() update_ec(ctx, select_rw) returned 0x10000001
[INFO ] VB2:vb2api_fail() Need recovery, reason: 0x26 / 0x1
[INFO ] VB2:vb2api_ec_sync() ec_sync_phase2(ctx) returned 0x10000001
[INFO ] Saving nvdata
[ERROR] EC software sync failed (0x10000001), rebooting
[INFO ] board_reset() called!
[INFO ] full_reset() called!
```
Change-Id: Id7bfa620e8c19d5b162b60e5cc37003ff339b589
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87427
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add implementation of sku_id function that reports the SKU ID
information by making use of ChromeOS EC host command. This function
can replace redundant sku_id function definitions across boards that
rely on ChromeOS EC host command to report the SKU ID information.
The boards that relying on ChromeOS EC host command for SKU information
without any board specific quirks can select EC_GOOGLE_CHROMEEC_SKUID
to make use of common sku_id function.
Brya, zork, rex, fatcat, brox and dedede boards select
EC_GOOGLE_CHROMEEC_SKUID to use ChromeOS EC sku_id function.
BUG=b:396366352
TEST=Verify zork and brya boot log reports the correct the SKU ID
information
Change-Id: I958cc88bf316dd2327b6545c5a37e8010e96c5d7
Signed-off-by: Aamir Bohra <aamirbohra@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
ChromeEC support information for SKU, OEM name and manufacturer name
using EC host commands. Instead of tying it up with SKU ID Kconfig
define a new Kconfig that clearly describes and allow adding support
for SMBIOS APIs based on ChromeEC host command.
BUG=b:396366352
TEST=Verify ec_smbios still compiles for required boards.
Change-Id: I665a3276aa6dc01571657359d17f292efc601d63
Signed-off-by: Aamir Bohra <aamirbohra@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86993
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch modifies the get_lid_switch() function to allow faking the
lid switch state when the GBB_FLAG_DISABLE_LID_SHUTDOWN Kconfig option
is enabled.
When GBB_FLAG_DISABLE_LID_SHUTDOWN is enabled, the function will
always return 1 (lid open), bypassing the actual lid switch state
retrieval from the Embedded Controller (EC).
This functionality is specifically designed to facilitate factory
processes, such as netboot image downloads, where devices need to
remain operational regardless of the lid's closed state. This prevents
intended shutdowns triggered by a closed lid during manufacturing and
testing.
By setting GBB_FLAG_DISABLE_LID_SHUTDOWN, we override the actual
lid status with a simulated LID status is open, which is a
prerequisite for display initialization.
w/o this patch:
```
[ALERT] Graphics hand-off block not found
...
[INFO ] NAME | PORT | POLARITY | VALUE
[INFO ] lid | undefined | high | low
```
w/ this patch:
```
[INFO ] NAME | PORT | POLARITY | VALUE
[INFO ] lid | undefined | high | high
...
[INFO ] framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
[INFO ] x_res x y_res: 1920 x 1200, size: 9216000 at 0xd0000000
```
BUG=b:333982806
TEST=Verified lid switch behavior with and without
`GBB_FLAG_DISABLE_LID_SHUTDOWN` enabled.
Change-Id: I89d506ab50b421b93be13b0e5e36a7ef1247e2b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86807
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In CB:86109 it was reported that some options incorrectly don't depend
on EC_DASHARO_EC. Remove `depends on` from all options and instead put
everything behind an `if EC_DASHARO_EC` to ensure options don't cause
issues with boards not using Dasharo EC.
Change-Id: If6303bf7f155749bfcf9145fb93b018247350009
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86698
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The EC code will monitor Body to choose corresponding DPTF oem variable
table. When it changes, this event will send to the ACPI FW through host
event and then pass onto the DPTF kernel driver.
BUG=b:394177292
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot
Change-Id: I7ed72157d3480fca5fd1a58b5d9bc3e321f4a628
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Because the AGAH EC code is based on monitoring adapter current to
choose the corresponding DPTF OEM variable table, but not every
project follows this design. Based on the comment below, the AGAH
EC code was removed in 2023, so remove the AGAH DPTF OEM variant,
allowing each OEM to adjust in EC ASL accordingly.
BUG=b:394177292
BRANCH=None
TEST=None
Change-Id: I2929eaa65a518b06f32e33cc31ae4a01bcfb77e8
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86493
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit renames the `google_chromeec_do_early_poweroff()` function
to `platform_do_early_poweroff()`, aligning it with the API that adds
early power off support using the Chrome EC.
It selects the `HAVE_EARLY_POWEROFF_SUPPORT` Kconfig option for platform
to perform early power off procedures.
Change-Id: I0c634d69de36fe8bdb6a61c121e321d3626ac3ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit implements the `google_chromeec_do_early_poweroff`
function for the Chrome EC. This allows the system to power
off before memory initialization by triggering an EC reset
with EC_REBOOT_COLD_AP_OFF.
BUG=b:339673254
TEST=Able to build and boot google/brox.
Change-Id: Ia53469feb2a020b38a5414728159b09c86c7e32d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86337
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Move all of the EC-related CFR options into a header in the ec
directory, so it can be reused across multiple boards.
TEST=build/boot starlabs/starbook_mtl,starlite_adl and verify CFR
options work properly.
Change-Id: I831559184de917b32e4993e8e34ffbc7b7e883e4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86318
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Desktop devices don't need and shouldn't define a lid switch.
TEST=build/boot starlabs/byte,starlite_adl
Change-Id: Iecf3e2558e244cc0bec301a505c0bc86684954aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Including the Virtual Button Driver made laptops report as a detachable
in tablet mode. Adjust how it's included, so they report as laptops.
Change-Id: Idc2076c400524744836e2f52124ccb8502622b04
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86315
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are not referenced anywhere, so remove them.
Change-Id: Ieb66099dcb9e13b26e6a7a752584537c060c8c18
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86317
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an option alongside the three existing curves to just turn
off the fan.
Change-Id: I39f6599056fe0116abbd7e2eb4084f77a7c395d3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
EC_DASHARO_EC_FLASH_SIZE is set regardless of whether the dasharo
EC is used. Add a dependency so it is only set when needed.
Change-Id: Icce0c7a31c89cea5e7bf89770dedbf82ff56170b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
A timeout when attempting to read/write to an EC should be treated as
an error, as it could potentially cause unwanted or unexpected behavior
from the device.
Change-Id: I60be6191dcd8ff576fa525f08720b6ea2d0a7454
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
For the Q events to be used, they need to sit under the EC device
in ACPI. Move them accordingly.
Change-Id: I58a41ae660ec466a08d4c290ff820b713b866f4f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Improve host EC command debugging with timestamps and duration for
better analysis, this feature can be enabled by selecting the config
EC_GOOGLE_CHROMEEC_HOST_CMD_DEBUG.
BUG=none
TEST=Brox/lotso device successfully built and booted. Debug messages
confirmed in device logs only when the specific configuration is
selected. Sample print: "EC HOST CMD Duration: 661 us, Command: 0x4b,
version: 0x0"
Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Move the Q-Events used by the merlin EC to their respective
files, i.e. `Q0B` for Battery Status Update to battery.asl.
This means that only revelant events will be included.
Change-Id: Ib41fbafd79b999409a520361a4d372902d878794
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85945
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove variant directories for boards that haven't or won't be
ported, or that now use the common "Merlin" code.
Change-Id: Ibfdd858c6460a1291d6a15bb7eccee9e9006adff
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit introduces an automatic linkage between the Microchip
EC (EC_GOOGLE_CHROMEEC_MEC) and ACPI memory
mapping (EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) options. This linkage is
enabled when the Microchip EC is selected.
Certain data registers in Microchip ECs cannot be accessed via I/O
space. Instead, an indirection mechanism is required for register
access. When using such an EC, coreboot must publish ACPI information
to access these data registers through ACPI data ports 66h/62h.
Analysis of the coreboot codebase has revealed that the
EC_GOOGLE_CHROMEEC_MEC and EC_GOOGLE_CHROMEEC_ACPI_MEMMAP options are
consistently used together. This commit streamlines this dependency by
linking the two options.
TEST=/sys/class/power_supply/BAT0/* reports consistent values on
fatcat board.
Change-Id: Ib4120a6d0ba2f4785e8b07b33943010e58bcbdd3
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85886
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is in preparation to store options in EFI variable store, rather
than CMOS. However, some still need to stay in CMOS, so that they can
be accessed via ACPI.
Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76582
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is done by edk2, so there isn't any need for coreboot to do it.
Change-Id: I947d5d2f7512cc910963054dfbe6b5dc0f00462a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add an option to set the Power LED to a lower brightness level
Change-Id: I39507d4f2e572ca31ad982ce0d730a0d00f6ca32
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85702
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ensure any reads or writes to the EC memory, are performed with ECRD
(Read) and ECWR (Write) as these methods use a mutex.
Also, use local variables to cache reads of the same variable within
a given ACPI method.
This solves:
Initialized Arguments for Method [ECRD]: (1 arguments defined for method invocation)
Arg0: 00000000967261a4 [RefOf] <Node> Name ECPS RegionField 000000007d4b8073
ACPI Error: Aborting method \_SB.PCI0.LPCB.EC.ECRD due to previous error (AE_BAD_PARAMETER) (20230628/psparse-529)
ACPI Error: Aborting method \_SB.PCI0.LPCB.EC.ADP1._PSR due to previous error (AE_BAD_PARAMETER) (20230628/psparse-529)
Change-Id: I0bbb538017cc004bff1989a8017ccfcd1ba9ab5c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84734
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow boards that use the merlin EC to disable the lid switch.
Change-Id: Ib5f71ce46e9e97a1a02e4ea5af6aeb094ee6fad7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84634
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow boards that use the merlin EC to configure the charging speed,
as all versions of the merlin EC support this.
All coreboot does it write a value to the EC RAM and the EC will
handle the rest.
Change-Id: I46faa540530c5bd7f5473021561380213158152e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Commit 50b7976bb2 ("ec/starlabs/merlin: Remove ITE mirror
functionality") removed the mirror_flag param from the EC code, but
some remnants were left behind in the platform and mainboard code.
Drop these unused bits.
TEST=build/boot starlabs/starlite_adl
Change-Id: I6eb8c9a6ef8f92e2d92081b8451cef8d7246ff7e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This change adds support for the generic LPC memory range configuration
in the EC ACPI code.
If CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is enabled, the
EC will use the generic LPC memory range for EMEM related communication
between EC and AP Firmware. This is useful for platforms that do not
have a dedicated IO range like accessed EMEM through port 62/66 or
through LPC at 900h.
The generic LPC memory range is defined by the _SB.PCI0.LPCB.GLGM()
method. This method returns the base address and size of the memory
range.
Update the comment section to reflect the alternative source for EMEM
data when CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is enabled.
BUG=b:354066052
TEST=Build and boot on a device with
CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE enabled.
Change-Id: I8038e2827ec7e301bad3a5a58df007f3a448bad7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces a new function,
google_chromeec_is_barrel_charger_present(), which checks if a barrel
charger is present.
The function uses the following logic to determine if a barrel charger
is present:
- If both a barrel charger and USB-C PD are present, then the barrel
charger takes precedence over USB-C PD. As a result,
google_chromeec_is_usb_pd_attached() will return false. This logic can
be used to deterministically say if a barrel charger is present even
when both a barrel charger and USB-C PD are attached.
- If an AC charger is detected and USB-C PD is not present, then a
barrel charger must be present.
This change allows the EC to accurately detect the presence of a barrel
charger, even when a USB-C PD charger is also attached.
BUG=b:377798581
TEST=Able to read the charger status correctly while booting
google/fatcat.
Experiment #1:
- USB-C PD Attached = yes
- Barrel Attached = No
- Charger Detected = Yes
```
fatcat-rev257 ~ # cbmem -c | grep -5 "ac_charger_present"
[INFO ] ac_charger_present: yes
[INFO ] usb_pd_present: yes
[INFO ] baseboard_devtree_update: Barrel Absent
```
Experiment #2:
- USB-C PD Attached = No
- Barrel Attached = Yes
- Charger Detected = Yes
```
[INFO ] ac_charger_present: yes
[INFO ] usb_pd_present: no
[INFO ] baseboard_devtree_update: Barrel Present
```
Experiment #3:
- USB-C PD Attached = Yes
- Barrel Attached = Yes
- Charger Detected = Yes
```
[INFO ] ac_charger_present: yes
[INFO ] usb_pd_present: no
[INFO ] baseboard_devtree_update: Barrel Present
```
Experiment #4:
- USB-C PD Attached = No
- Barrel Attached = No
- Charger Detected = No
```
[INFO ] ac_charger_present: no
[INFO ] usb_pd_present: no
[INFO ] baseboard_devtree_update: Barrel Absent
```
Change-Id: I9644f0dec057f95bb0a22cdc18edc1a0234ee3a9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch adds a new API `google_chromeec_is_below_critical_threshold()
` to check if the battery level is below the critical threshold.
The API uses the existing `ec_cmd_battery_get_dynamic()` command to
retrieve the battery flags and checks the `EC_BATT_FLAG_LEVEL_CRITICAL`
flag to determine if the battery level is critical.
This API can be used by other components to query the battery critical
status and take necessary actions, for example, while the system is
booting with low battery fuel with and/or without an AC
charger attached.
This addresses the need to implement a low battery charger icon and
detect when the system is booting with low battery fuel. The existing
`google_chromeec_is_battery_present_and_above_critical_threshold()`
API is not suitable for this purpose because any negative decision
(like battery not present and/or battery is critically low) implemented
around this existing API will also render the lower battery indicator
when the system is booting into battery cut-off mode. Ideally, we do not
wish to render any icon and simply allow boot to the OS during system
battery cut-off boot.
BUG=b:377798581
TEST=Able to read the battery status correctly while booting
google/fatcat.
Change-Id: Id1fc1df374fb4c663becc371c69b285d8b9957ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85759
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch introduces a new API, `google_chromeec_is_charger_present()`,
to determine if a charger is connected.
The API leverages the existing `ec_cmd_battery_get_dynamic()` command
to retrieve battery flags and checks the `EC_BATT_FLAG_AC_PRESENT`
flag to ascertain charger presence.
Other components can leverage this API to query the charger status,
which is particularly useful for distinguishing between barrel chargers
and USB-C chargers after relying on the
`google_chromeec_is_usb_pd_attached()` API.
BUG=b:377798581
TEST=Able to read the charger status (w/ barrel and/or w/ USB-PD)
correctly while booting google/fatcat.
Change-Id: Iadf81400f71a51c093f71fe995cacc107c50c7af
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85758
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change introduces a new API, `google_chromeec_is_usb_pd_attached()`
which checks the current status of the USB-C port and returns whether a
USB Power Delivery (PD) charger is currently connected.
This API is useful for determining if the system is currently being
powered by a PD charger.
BUG=b:377798581
TEST=Able to read the PD status correctly while booting google/fatcat.
Change-Id: I47c934ee8a7563d4ba5124bff5613e61dd66e923
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add support for indexed IO for ec communication, Indexed I/O allows
memory access using a single I/O port base address usually called an
index register and another port address called a data register.
BUG=b:379224648
TEST= able to build nissa/trulo.
Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch adds support for the Intel Virtual Button driver, which
reports whether a tablet is docked or undocked. The GPIO used for
detection is hardcoded to GPP_F15 for now, specific to the
`mb/starlite_adl` board.
The GPIO value is returned to the HID driver via the `_STA` and
`VGBS` methods. These methods ensure proper notification to the OS,
allowing it to show or hide the virtual keyboard depending on the
docking status.
Tested on `starlite_adl` with Ubuntu 24.04, confirming the virtual
keyboard appears when the tablet is undocked and hides when docked.
This was verified with ACPI debug enabled, as dmesg does not
report the state of the GPIO.
Change-Id: I574a1b2d3907b2341a0dfdc412151d574ba4848e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83879
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change allows the Chrome EC (CREC) ACPI device to publish the LPC
Generic Memory Range (GMR) address range using the _CRS method.
The Google CREC driver can now parse this information to determine the
MMIO address map, enabling access to the LPC GMR register space.
This addresses the issue where the CREC driver was unable to
automatically determine the LPC GMR base address.
TEST=Able to build and boot google/brox.
without this patch:
brox-rev0 ~ # cat /proc/iomem | grep fe0
fe000000-fe00ffff : INTC1026:00
fe000000-fe00ffff : intel_scu_ipc
fe03e000-fe03efff : 0000:00:1e.0
fe03e000-fe03e1ff : lpss_dev
fe03e000-fe03e1ff : serial
fe03e200-fe03e2ff : lpss_priv
fe03e800-fe03efff : idma64.4
fe03e800-fe03efff : idma64.4 idma64.4
with this patch:
brox-rev0 ~ # cat /proc/iomem | grep fe0
fe000000-fe00ffff : INTC1026:00
fe000000-fe00ffff : intel_scu_ipc
fe03e000-fe03efff : 0000:00:1e.0
fe03e000-fe03e1ff : lpss_dev
fe03e000-fe03e1ff : serial
fe03e200-fe03e2ff : lpss_priv
fe03e800-fe03efff : idma64.4
fe03e800-fe03efff : idma64.4 idma64.4
fe0b0000-fe0bffff : GOOG0004:00
Change-Id: Ib3ea3e2a482f9eceaa8c15e38b7e708b156bc978
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85603
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change simply replaces 0x80 with a top level constant called
ACPI_NOTIFY_CROS_EC_MKBP. There are no functional changes.
BUG=b:343288326
TEST=Build
Change-Id: Ia476263620acc269f9dd8a6b3c9e5e247b403aee
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Add API to get Power Delivery (PD) Chip info which includes vendor ID,
product ID and firmware version(if any).
BUG=None
TEST=Build Brox BIOS image and boot to OS.
Change-Id: I4cc4493ac64d44076877fee633488c95cd09807e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add support to define ACPI devices for USB-C ports using UCSI. When
defining the typec configuration do not set mux/retimer information.
cros_ec_ucsi does not support setting USB muxes.
BUG=b:349822718
TEST=emerge-brox coreboot chromeos-bootimage. Boot to OS on brox,
confirmed that there are ACPI devices for each USB-C port and
cros_ec_ucsi correctly matched the ACPI devices ("ls -l
/sys/class/typec" with an update to add an ACPI match table to
the cros_ec_ucsi driver).
Change-Id: Ie7c281fe2a7fab705d3c238dcc4be68c93afd652
Signed-off-by: Jameson Thies <jthies@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84404
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit refactors the long battery string implementation to include
caching of the EC response for battery information (model, serial, and
manufacturer).
This optimization reduces resume time by approximately 63ms by
minimizing communication overhead between the AP and EC.
BUG=b:366338622
TEST=Verified on google/tivviks_ufs:
* Long battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING is enabled.
* Short battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING=n.
Change-Id: I32ae5b5e618f20335f3d344811a97f1416df529e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Older ChromeOS devices (pre-CR50) do not support reading long battery
strings. This commit adds a Kconfig option,
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING, to enable or disable this
feature.
This allows devices with TPM_GOOGLE (CR50/TI50) to read and display
long battery strings, while older devices like google/link, wolf, samus,
and chell will continue to display only the first 8 characters.
This change ensures compatibility with older devices while enabling
the display of complete battery information on newer platforms.
BUG=b:366338622
TEST=Verified on google/tivviks_ufs:
* Long battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING is enabled.
* Short battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING=n.
Change-Id: I7859809278b7e926bbe8beb1a0a9e12c7e6c220d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84352
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reporting the battery serial number to ACPI causes Windows to say
there isn't a battery present. As the serial number is as useful as
waterproof towel, don't do it.
Change-Id: I97a28b1d8d7bb45ea4790c8125cd3c1bc52ee5f9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
