Set the UPD `TcNotifyIgd` to `2` (Auto), so that the TCSS subsystem
will notify the Integrated Graphics of display changes.
Change-Id: I2b47a534f0816545fe58bde8963c56f0455871eb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89054
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a new Kconfig option, `HAVE_CBFS_FILE_OPTION_BACKEND`, to
explicitly select the capability of using a CBFS file for option
storage.
This capability is currently only used by ChromeOS boards leveraging
FSP 2.0. By decoupling the capability check from the choice default
selection logic, we can simplify the configuration of the option
backend choice:
- The new capability config is set to 'y' only if `CHROMEOS &&
PLATFORM_USES_FSP2_0`.
- The 'Option backend to use' choice now depends on this new capability
config.
This change allows other SoC platforms beyond Intel to leverage this
feature.
TEST=Build all ChromeOS FSP 2.0 boards and confirm the default option
backend is still USE_CBFS_FILE_OPTION_BACKEND.
Change-Id: Ia55e0feae8fd462411ed3e9306d19ed6d1cfcaf1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add H58G66BK8BX067 memory part as DRAM ID 2.
BUG=b:445200980
TEST=None
Change-Id: Ica4c253ebed922f204e4782bbfeb1f09f12f5723
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Table is from vendor. Update HWEQ and AGC setting.
BUG=b:435345756
TEST=emerge-brox coreboot
check system audio output is fine
Change-Id: I0869a4902e38e8010274769de7f8e7b9a4160aae
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Disable eMMC related GPIO pins via firmware config on non-eMMC skus
BUG=b:443202137
TEST=flash and boot successfully on all kaladin SKU
Change-Id: Ia98702368208649fc0891417c7e8c6c3685d40be
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89069
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`dt_add_reg_prop` and the newly introduced `dt_add_iommu_addr_prop`
share identical logic for building the binary data buffer, differing
only in the property name written to the Device Tree. Therefore,
refactor the shared logic into a new static helper function,
`dt_add_addr_and_size_prop`.
The existing `dt_add_reg_prop` is converted to a wrapper around this new
helper.
`dt_add_iommu_addr_prop` is introduced as a separate wrapper to
specifically add the `iommu-addresses` property. This property defines
reserved IOVA ranges or identity-mapped regions, such as a display
framebuffer configured by the bootloader. It is typically utilized
within the `reserved-memory` subsystem.
BUG=b:435289727
TEST=The below translation fault does not occur.
[ 0.171028] arm-smmu-v3 30800000.iommu: TBU_id-2-fault_id:0x2000008(0x8), TF read in NORMAL world, iova:0xa3000000, sid:144, ssid:0, ssidv:0, secsidv:0
Change-Id: Icedcce5681a7b659b11b7e7208663bc1d920ce3b
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89152
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Realtek ALC1320 as speaker Amplifier.
Use ALC721 as codec and ALC1320 as Amplifier on SoundWire Link 3.
BUG=b:442964982
TEST=emerge-fatcat coreboot
1.Set fw_config AUDIO bits to AUDIO_ALC1320_ALC721_SNDW
2.check the SSDT.dsl:
PCI0.HDAS.SNDW including 0x000331025D072101 & 0x000332025D132001
Change-Id: I4c6b5c3f2d9acb7eaf8f77844526bc9de3ae1f99
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89177
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the VNC18 regulator API for the MIPI panel usage.
BUG=b:432353024
BRANCH=skywalker
TEST=Use an oscilloscope to confirm that the regulator’s output
voltage is 1.8V.
Change-Id: Ib2065d8b4f92f4ad266976883cb2927107330a69
Signed-off-by: Niklaus Liu <niklaus.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89172
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
To provide power to MIPI panel, add support for regulator VCN18.
BUG=b:432353024
BRANCH=skywalker
TEST=Use an oscilloscope to confirm that the regulator’s output
voltage is 1.8V.
Signed-off-by: Niklaus Liu <niklaus.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I4d90b3c053f1a06ae0c65d6ce6d800c22d6d3442
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89171
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a flag "USE_SYSTEM_CMOCKA" in the Makefile of tests. (default 1)
If USE_SYSTEM_CMOCKA=1, we will check if the system has Cmocka module,
and link it directly. If the system doesn't have Cmocka, we will set the
flag to 0 and print a warning message.
If USE_SYSTEM_CMOCKA=0, we will build Cmocka from 3rdparty source code.
BUG=none
TEST=make unit-tests -j
TEST=USE_SYSTEM_CMOCKA=0 make unit-tests -j
BRANCH=none
Signed-off-by: roccochen@chromium.com <roccochen@chromium.org>
Change-Id: I091784ca541e2590e3db0a18ceea83e7895ed0c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79019
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use fw config bit 29 to identify different ish files in pujjolo
when ISH_PRESENT and pujjoquince when ISH_ABSENT.
ISH_PRESENT : pujjolo_ish.bin
ISH_ABSENT : lite_ish.bin
BUG=b:437881361
TEST=Build and boot to OS, check pujjolo and pujjoquince load
corresponding ish file using command ectool --name=cros_ish version and test warmboot/coldboot/suspend pass.
Change-Id: I61b90881abcad368dd668f2631f061b0ea00b57f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
GPP_B23 and GPP_A15 GPIOs in Felino design being used for MEM
straping selection but Felino supports only one mem id (index 0)
hence, these GPIO reads were never needed in felino code.
The GPP_A15 and GPP_B23 pins on the Fatcat mainboard variant Felino
are no longer used. Update the GPIO table to reflect this and
explicitly set the pins to not connected (NC) as per schematics
dated 08/30.
TEST=Able to build and boot google/felino.
Change-Id: I9d8ed19aab612f7104227544c24c37d19024cfb0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The GPP_A15 pin on the Fatcat mainboard variant Lapis is not used,
according to schematics dated 08/30.
Update the GPIO table to reflect this and explicitly set the pin to
not connected (NC).
TEST=Able to build google/lapis.
Change-Id: Ib89421952f5844283809fe99a902e36a17f55fae
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89154
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
These are not programmed by coreboot, so drop them.
Change-Id: If7b371aa6f64a7f034344a6e926ca0662fa717c2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
These are not programmed by coreboot, so drop them.
Change-Id: Id3f870c531f0cfd078c899953ff65b406e7e5bb6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89138
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are not programmed by coreboot, so drop them.
Change-Id: I1ad4f33565ce1d5a67ac7f066fd5140a7cb2faf8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
These are not programmed by coreboot, so drop them.
Change-Id: Ifdcbb52cf1823692296775895130fcec8be59c85
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
These are not programmed by coreboot, so drop them.
Change-Id: If1c68f183012d78b3e8847e8fe103280fe0103ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
These are not programmed by coreboot, so drop them.
Change-Id: I577634eef5e0f218be81323bbd5c6d8a0651549c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89134
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add H58G66BK7BX067 memory part as DRAM ID 1.
BUG=b:443646405
TEST=None
Change-Id: I3ab13e65b94dd4b46ed788df31085c9013d84848
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89158
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Set disable_progress_bar to disable the memory progress bar for ocelot
board as this is an OEM feature and might not be used by all.
TEST=Verify that ocelot builds without any error
Change-Id: Ifef7a2645dce696f32cea42fd928a1f858fd0333
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit modifies the Ocelot mainboard configuration to ensure the
Audio controller is only enabled when a valid `FW_CONFIG` is selected.
This change introduces audio probe statements that allow the
system to boot successfully even if `FW_CONFIG` is set to
`AUDIO_UNKNOWN`, effectively disabling the audio controller in such
cases.
This prevents potential boot failures when an unsupported or unknown
audio codec is selected, improving system robustness.
BUG=b:412736286
TEST=Verify that ocelot builds without any error
Change-Id: I7c125c67b70a0e0f3df3629cb0002bfdaa57fdc9
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88938
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Apply a `logo_bottom_margin` of 100 pixels to the `common_soc_config`
for Ocelot. This configures the OEM footer logo to be rendered 100
pixels above the bottom edge of the screen.
Change-Id: Ia7436ab267f91771ee2c0e91743ddaf43280cc87
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88936
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments.
TEST=build/boot Win11, Ubuntu 25.04 on Starbook RPL, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.
Change-Id: I54fb60026de953db7dc85ee64823b9584af04a69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89060
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Update the verb count.
TEST=build/boot Win11, Ubuntu 25.04 on Starfighter RPL, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.
Change-Id: I2b96318df4431bc155af5a8f92935900031e0bfa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Update verb count. Add HDA verbs for Intel IGD HDMI audio
output.
TEST=build/boot Win11, ubuntu 25.04 on Starbook TGL, verify all audio
inputs/outputs function as expected. Verify verbs loaded via cbmem log.
Change-Id: Id9a08c8bd32e0c75f92e8d6b3b8ff6c033608a4f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments.
TEST=build/boot Win11, Ubuntu 25.04 on Starbook RPL, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.
Change-Id: I4ccc604f7db4ec85d8e5f311c7f8fd5c913ec04b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89082
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Group raw verbs in sets of 4 to make verification of verb
count easier.
TEST=build/boot Win11, ubuntu 25.04 on Starbook MTL, verify all audio
inputs/outputs function as expected. Verify verbs loaded via cbmem log.
Change-Id: I0805d943009de1963c8e6da5acf56dd7a5ea83ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89081
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Group raw verbs in sets of 4 to make verification of verb
count easier.
TEST=build/boot Win11, Ubuntu 25.04 on Starbook KBL, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.
Change-Id: I3cf96ce12250d6a5cd7afa39070681606266fb2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Update the verb count.
TEST=build/boot Win11, Ubuntu 25.04 on Starbook CML, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.
Change-Id: I1ee05afe9805ca6531d49150f1ead8722c4393b2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89079
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Group raw verbs in sets of 4 to make verification of verb
count easier.
TEST=build/boot Win11, Ubuntu 25.04 on Starbook ADL-N, verify all audio
outputs working as expected. Verify verbs loaded via cbmem log.
Change-Id: Ie0961a6ebc4aa8df0c2fedeff8fd5bacd16fc01e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89078
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments.
TEST=build/boot Win11, Ubuntu 25.04 on Starbook ADL, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.
Change-Id: I728c835361f1fa6fe813255973b33131e2a008e2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit adds support for a new Panther Lake B0 SKU CPUID c06c3.
BUG=b:444497427
TEST=Successfully boot a fatcat device with new Panther Lake B0.
coreboot displays the following log:
CPU: ID c06c3, Pantherlake B0, ucode: 0000010c
Change-Id: Id2c1caf8d6845bb16a94314c4e9a214def06efee
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89150
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This requires version of EDK2 in use to understand those defines, but
the build isn't affected negatively if they aren't handled.
Upstream EDK2 has CAPSULE_SUPPORT for a while and modifications that
make it enable FMP capsules are already merged to be part of the next
stable release (the one after edk2-stable202508 which should be
edk2-stable202511).
The `sed` part is updated because GUID contains dashes just like option
names, so need to take leading spaces into account to avoid processing
dashes in values. This doesn't cover all possible cases, but should be
good enough.
Change-Id: I1c684cb8929842a5d3c4b06e8a9c0a748470ea41
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
SlowSlewRate, AcousticNoiseMitigation and FastPkgCRampDisable upds
can be overwritten with this patch.
BUG=none
TEST=Able to override the acoustic noise UPDs.
Change-Id: I5bfa98834f8d7cfcaab3fdbb7dde914d78529581
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Kelsier shares the same firmware with Kaladin so coreboot loads the same
loader firmware to ISH. Since Kelsier is a sensor-less design, change
it to load lite_ish.bin and disable ISH related GPIOs depending on
firmware config.
BUG=b:441613379
TEST=flash and boot to DUT, check suspend function works normally on
kelsier
Change-Id: I04c77db813fcd993217b5c366872cc583e265939
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Add mapping of different SKUs based on CPU ID and TDP values.
Add PowerLimits (PL) values.
Add i_trip value for Fast Vmode.
Note: The i_trip value, the value at which the Voltage Regulator (VR)
or SoC will trigger a protective action such as throttling or
entering Fast Vmode is, due to not being documented, currently set at
70% of the maximum current the VR is designed to support for a rail.
The actual i_trip value to be updated once it is available.
Ref=858124 Power Delivery Guide Rev1p0
830097 Powermap Rev1p1
BUG=b:433211504
TEST= Build Ocelot and verify it compiles without any error.
check CPU log for the following error
[ERROR] Could not find the SKU power map
With the current patch this error line is not seen in the CPU log
anymore.
Change-Id: I8c54efc8eb360ed6f814a336448bb204d5ab0268
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88858
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
As per Intel document 853127, EPD_ON_GCD_OUT (previously GPP_A15)
is no longer available for other functions. Updated GPIO
configuration accordingly.
Reference: Intel doc 853127
BUG=none
TEST=Build and boot test on fatcat hardware
Change-Id: Ie4a3967ceecd10905ba0424d85d8f1392625bf16
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89103
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the matsu variant of the ocelot reference board by copying
the ocelot files to a new directory named for the variant.
BUG=b:443612246
TEST=1. util/abuild/abuild -p none -t google/ocelot -x -a
make sure the build includes GOOGLE_MATSU
2. Run part_id_gen tool without any errors
Change-Id: I81d010fdda927db56d7b41ddc527c1c40b2cf768
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Update GPIO_PCH_WP configuration for trulo varaints as the value
in the baseboard is changed.
BUG=b:443677716, b:435612546
TEST=Build uldrenite, pujjocento and orisa firmware successfully
Change-Id: I7fb35091000b1df1b8008f26488e9290be3efe2d
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Change GPIO_PCH_WP from GPP_E3 to GPP_E12 to align with trulo
reference hardware schematic.
BUG=b:443677716, b:435612546
TEST=Build pujjolo and kaladin firmware and verify SPI ROM
write-protect
Change-Id: I935d74cb5447f45f297fe45506c14623095d7127
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89117
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change stylus gpio and wake source setting to let eventlog could
show GPE #12 message when interrupt suspend by stylus.
BUG=b:439761057
TEST=Build and boot to OS, do the suspend_stress_test and check
eventlog show wake source information. And do warmboot/coldboot/
suspend 500 times stress test all pass.
Change-Id: I8d16e867fd56f1072b09bb6ab71b6d08a7d38376
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89129
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
Uldrenite14 need to set this config since we use unified firmware
for UFS and eMMC skus.
BUG=b:437006063
TEST=emerge-nissa coreboot
Change-Id: I86f41a4e6c9c136f031eb3813efa3c06043237b9
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88932
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a wake configuration to the cnvi_bluetooth device for
all the ptlrvp board variants. The "wake" setting is now registered to
"GPE0_PME_B0" using the common CNVi block. This enhancement ensures that
the cnvi_bluetooth device can properly wake the system.
TEST=Able to wake up the device from a low power state using a keyboard
Bluetooth device.
Change-Id: I4c17ca926a4409cedfaef24a802330ef463703ac
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
