This case doesn't reflect an error condition, so adjust the printk
level accordingly.
Change-Id: I3afa818447d3e7c9d08968ffc6b57a663af45c3e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88011
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The generic device attached to this driver doesn't have resources
separate from the parent device to which it's attached, so
use 'noop_read_resources' to suppress a false-positive error in
the cbmem console log (GENERIC: 0.0 missing read_resources).
Change-Id: I985318dcc7cc32aaa3f6a599ade95e065900031e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88012
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Anx7625 reads EDID through AUX channel with I2C Over Aux operation,
reading 16-byte chunk a time. Sometimes, panel(CSOT MNB601LS1-3)
does not returns EDID raw data in time or returns OK without providing
data.
Root cause:
The measured difference between two adjacent UI signals of the AUX
signal is 36ns (518 - 482ns), it meets the VESA DP1.2/1.3 spec < 0.08UI
(48ns) requirement. However, this value exceeds the VESA DP1.1a spec
supported by the panel: max < 0.04UI (24ns) requirement, which exceeds
the tolerance value of the panel and leads to EDID communication
failure.
To address this issue, determined by tests, so that the issue did not
reproduce in over 200 tests
Test result:
Verified on 12pcs panels(8pcs issue panels, 4pcs new panels), 10pcs
tested 300 cycles, 2pcs tested 400 cycles, issue cannot be reproduced.
BUG=b:415946451
TEST=Tested on corsola over 200 times
BRANCH=corsola
Change-Id: I2d4f6b65b8f663ea9b9459e0343897a1223d631a
Signed-off-by: Xin Ji <xji@analogix.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Use POSTPONE_SPI_ACCESS to handle elog data later boot phase to avoid
flash access delay by other boot controllers.
Intel has pre-CPU boot controllers (e.g. CSE) which load non-CPU
firmwares. Boot-critical firmwares are loaded before CPU reset and
non-boot-critical firmwares are loaded during CPU boot. If another
controller accesses SPI to load firmwares, reading SPI by CPU is ok,
but writing to SPI for saving elog data can take ~32ms sometimes.
Saving elog data usually takes less than 1ms.
There are three elog handling sequences that need to move together
under the Kconfig:
- Soc folder
- Elog driver folder
- ChromeOS folder
Before this change, sometimes it delays like below:
BS: callback (0x7386d428) @ src/soc/intel/pantherlake/elog.c:216 (32 ms)
After this change, the delay is less than 1 ms:
BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms)
TEST
1. Enable DEBUG_BOOT_STATE
2. Check time
BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms))
Change-Id: I3f5e7acf5204e213179664d0d77151d415d00896
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit adds a new timestamp, `TS_FIRMWARE_SPLASH_RENDERED`
(ID 557), to precisely mark the moment the firmware splash screen has
finished displaying.
The timestamp is recorded in `src/drivers/intel/fsp2_0/silicon_init.c`
within the `do_silicon_init` function. It's conditionally added based on
the platform's configuration:
- For platforms using FSP's native BMP rendering (prior to FSP 2.2, with
`CONFIG(BMP_LOGO)` and without
`CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)`).
- For platforms where coreboot handles BMP rendering (`CONFIG(BMP_LOGO)`
and `CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)`).
This enhancement provides better visibility into the boot process and
allows for more accurate performance analysis related to splash screen
display time.
BUG=b:418935715
TEST=Able to build and boot google/fatcat. Verified below details in
`cbmem -t`.
```
557:Firmware splash screen rendering finished 47,193,590 (2,235)
```
Change-Id: Ibef967dbc6e224741438e9708b42486ba03d0104
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87812
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I am using a pair of Winbond W25Q64JVSSIM SPI flash chips for
coreboot development. While working on Asus P8x7x Series
autonomous soft strap update support, aka CB:85413 and CB:87334,
I found that without its signature (mfgr 0xef, dev 0x7017) added,
rdev_writeat() would fail to get anything into the flash chip
even though it reports success. Its other parameters are copied
from W25Q64_V as the two are almost the same.
Change-Id: I4af6268a2a1bde4d2ff9c76879c3bc59b91a916d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit refactors the code by eliminating unnecessary NULL pointer
checks for the `efi_bmp_image_header header` parameter in several
functions. The calling function `fsp_convert_bmp_to_gop_blt` already
verifies that the `header` pointer is not NULL before invoking these
functions, rendering these checks redundant. Similarly, checks for
`adjusted_x` and `adjusted_y` in `calculate_adj_height_width` have been
removed. This streamlines the code and reduces unnecessary operations.
Additionally, the `is_bmp_image_compressed` function has been simplified
for improved readability by directly returning the result of the
compression type comparison.
Change-Id: Ia8afcac0fb21633e379f5d8b9713ba6f8b92c1c8
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87616
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add IDs from the EDS, with a couple extras:
- eSPI: EDS says 0x7202, but our boards show 0x7702
- GT: Value changes between 0x7d51 and 0x7dd1 based on DIMMs installed
Change-Id: I8430914edd02954cbb38592bff896733b01c735d
Ref: Intel Arrow Lake-H/U EDS, Volume 1 (#777369, rev 2.0)
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87131
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
MRC cache used to be measured as runtime data when it was resided in
CBFS before commit 82aa8338c7 ("drivers/mrc_cache: Always generate an
FMAP region"). This patch will restore this behavior for MRC cache
stored in FMAP region outside of CBFS.
Now, MRC cache will be measured at the end of
mrc_cache_load_current(), mrc_cache_current_mmap_leak() and
update_mrc_cache_by_type(), to guarantee that a tamper with the memory
(like https://badram.eu/ ) will be detected, controlled by Kconfig
option TPM_MEASURE_MRC_CACHE.
TEST=On Ivy Bridge platforms, Empty MRC cache is not measured.
Changing DIMM causes both the old cache and new cache being
measured, thus the runtime data measurement is changed, which
could be used as an alarm for memory tampering. Starting from the
second boot after changing DIMM, the runtime data measurement
becomes stable.
Signed-off-by: Ivan Kuzneczov <ivan.kuzneczov@hardenedvault.net>
Change-Id: I0d82642c24de1b317851d0afd44985195e92c104
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The get_color_map_num function previously returned 0 for both error
conditions (e.g., NULL header, invalid image offset) and for BMPs
that legitimately lack a color map, such as 24-bit BMP logo. This
ambiguity prevented the correct processing of 24-bit BMPs for
firmware splash screens, as the caller could not distinguish them
from malformed images.
This commit addresses this by refining error handling:
1. Modifying `get_color_map_num` to return -1 for actual errors.
2. Ensuring a return value of 0 from `get_color_map_num` now
unambiguously signifies that the BMP has no color map. This
is relevant for formats like 24-bit or 32-bit, where the
default switch case now explicitly sets the color map count to 0.
3. Changing the function's return type and its internal color map
count variable (`col_map_number`) to `int` to accommodate the
negative error code.
4. Updating the caller, `fsp_convert_bmp_to_gop_blt`, to check for
a return value `< 0` to identify errors, separating these from
the valid no-colormap case (return 0).
These changes enable the successful rendering of 24-bit BMP images
as firmware splash screens. This also provides more robust BMP
parsing and clearer error distinction overall.
BUG=b:410318591
TEST=Able to build and boot google/fatcat. Verified 24-bit
BMP logo is able to render successful.
Change-Id: I7006e823e10b9892da17ff904095ef5892bb690d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87581
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the SMMSTOREv2 only supports MMIO ROM below 4GiB. As the
space below 4GiB is typically limited on x86, add support for extended
MMIO ROM windows as found on recent hardware.
Allow the SMMSTOREv2 to be memory mapped above 4GiB by adding a new
field to the coreboot table called 'mmap_addr'. The users outside
of coreboot must check the size field of the coreboot struct to
determine if mmap_addr is supported. When it is it holds the
64-bit physical address to the MMIO ROM window.
The old 'mmap_addr' was renamed to 'mmap_addr_deprecated' to indicate
that it should not be used any more.
Change-Id: I1131cfa5cdbf92bbd33de3e5b22a305136eec9f7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87114
Reviewed-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This commit implements coreboot native logo rendering when
`USE_COREBOOT_FOR_BMP_RENDERING` Kconfig is enabled.
When enabled, this option allows coreboot to perform the boot logo
rendering directly after the FSP initializes the display. A new API
`soc_load_logo_by_coreboot` is introduced for this purpose.
This approach offers greater flexibility for platform-specific logo
customizations (e.g., alignment) that might be impractical to
implement within the FSP.
Note that enabling this option might introduce a slight delay (~10-30ms)
in displaying BMP images compared to FSP-based rendering.
BUG=b:409718202
TEST=Built and booted google/fatcat. Verified boot splash was rendered
by coreboot as `USE_COREBOOT_FOR_BMP_RENDERING` was set to `y`.
Change-Id: I9454d0941458e29a5533a92170831f360765b413
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87541
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch introduces `USE_COREBOOT_FOR_BMP_RENDERING`, a Kconfig option
allowing platforms to choose coreboot to use its native bitmap (BMP)
logo image rendering and skip using the FSP for this purpose during
the boot process.
By default this option is disabled (default 'n'), therefore, the FSP
is utilized for displaying the BMP logo by populating the necessary
FSP UPD parameters.
Select this option for platforms that will use a coreboot native
implementation for BMP rendering (note: the native coreboot rendering
path is still under development/to be implemented).
This Kconfig provides the switch for such future integration.
Key changes:
- A new boolean Kconfig `USE_COREBOOT_FOR_BMP_RENDERING` is added under
`drivers/intel/fsp2_0/Kconfig`. It depends on `BMP_LOGO` and
defaults to 'n'.
- The help text clarifies that selecting this option will skip FSP-based
BMP rendering. Deselection implies a fallback to the FSP based
implementation.
- The function `soc_load_logo`, previously responsible for populating
FSP UPD parameters for the logo, is renamed to `soc_load_logo_by_fsp`.
This clarifies its role is specific to FSP-driven logo display.
- The call to `soc_load_logo_by_fsp` in `fsp2_0/silicon_init.c` is
now conditional on `CONFIG(BMP_LOGO)` being enabled but the new
`CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)` remains disabled.
- Implementations and calls to the renamed function are updated across
relevant SoC directories (AMD Mendocino, Intel Alder Lake, Apollolake,
Cannon Lake, Meteor Lake, Panther Lake, Skylake).
This change offers platforms greater flexibility in managing BMP logo
display, allowing them to either leverage FSP capabilities or integrate
with coreboot's native methods as they become available.
BUG=b:409718202
TEST=Built and booted google/fatcat. Verified boot splash was rendered
by FSP as `USE_COREBOOT_FOR_BMP_RENDERING` was set to `n`.
Change-Id: Ieda085df02263b9bf4bdd8f5d0e2137bef75def9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87513
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch moves `struct hob_graphics_info` and `fsp_graphics_info_guid`
into the FSP header file.
This change allows other coreboot APIs to utilize this information for
locating FSP graphics-related data to know the display resolutions and
other useful information (required for coreboot native implementation
of rendering splash screen).
BUG=b:409718202
TEST=Able to build and boot google/fatcat.
Change-Id: I445a4efa59769f25c93fc61ad1d15857716f5247
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87538
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The fsp_gop_blt.h header includes `enum lb_fb_orientation`. This enum
is defined within `<boot/coreboot_tables.h>`.
This commit adds the necessary include directive to ensure that
`enum lb_fb_orientation` is available.
BUG=b:409718202
TEST=Able to build and boot google/fatcat.
Change-Id: I0e432bef13ab1425c29e9ca4a82b06ff264a8613
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87537
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This makes Bluetooth RTD3 runtime configurable.
Change-Id: I467634e013a140e0a39802d2a1767583ba33a76e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
On mainboard/asus/p8z77-v_le_plus, programmed MAC address is being
reverted with controller resets done at loading and unloading of Linux
r8169 kernel module.
Ghidra examination of vendor BIOS reveals an additional sequence to
program the MAC address into its ERI register block. This patch
adds code to replicate that sequence, gated by a Kconfig so it's
only included where necessary.
BUG=https://ticket.coreboot.org/issues/579
TEST=When applied with mainboard level changes in CB:87437, specified
MAC address now recognized and retained by Linux r8169 driver without
further work.
Change-Id: Iae33e24e564f9fba52acb16138fe89085d9eeb03
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87436
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds Wildcat Lake-specific CPU and PCIe device IDs to the
header files and driver-specific code.
Reference:
Wildcat Lake Processor Prelim External Device IDs (820363)
BUG=b:394208231
TEST=Verified on Wildcat Lake Simulation Platform
Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87262
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since CFR options require a backend to store the keys/values, select
DRIVERS_EFI_VARIABLE_STORE when edk2 is used as the payload and
SMMSTORE is enabled, so that boards only need to select
DRIVERS_OPTION_CFR in order to have a fully-functioning configuration
setup.
TEST=build samsung/stumpy with DRIVERS_OPTION_CFR selected and edk2
payload used.
Change-Id: Ib8565e4fefb1b3f05e58ab039be8ab0d1bc046f1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
DRIVERS_EFI_FW_INFO requires some Intel vendorcode headers which are
selected by default on FSP 2.x platforms, but not by earlier ones.
Select the oldest UDK binding for non-FSP 2.x boards, so that the
required headers are available, rather than depending on UDK_BASE
and requiring those boards to manually select the binding
Change-Id: I27ab64ab0c9d4d45cc09061f6f8c3725c24df706
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
DRIVERS_EFI_VARIABLE_STORE requires some Intel vendorcode headers which
are selected by default on FSP 2.x platforms, but not by earlier ones.
Select the oldest UDK binding for non-FSP 2.x boards, so that the
required headers are available, rather than depending on UDK_BASE
and requiring those boards to manually select the binding.
TEST=build samsung/stumpy with EFI variable store support, without
manually selecting UDK_2017_BINDING at the mainboard level.
Change-Id: I099d3cc7690a0faecfe32a8bc814766c67c63fbb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87408
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With DRIVERS_EFI_UPDATE_CAPSULES enabled and when at least one capsule
was found, SMMSTORE SMI handler can use commands with the highest
bit (0x80) set to access the whole flash instead of just the SMMSTORE
region. The rest of the interface is identical to regular SMMSTORE v2
except for a new call to control full flash access.
The added call saves information about the availability of capsules in
SMM memory. The call is ignored when run more than once, meaning there
should be no way of enabling full flash handling after it was disabled
and vice versa. The call should always be made by the firmware to lock
further calls, so that an OS could not gain full flash access. This is
done on entry to BS_POST_DEVICE after capsules are obtained in
BS_DEV_INIT.
Change-Id: I7f3dbfa965b9dcbade8b2f06a5bd2ac1345c7972
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
It's an ACPI spec violation for a device to have both an _ADR and
a _HID method, so prefer the latter if a HID value is specified
via the chip registers.
Change-Id: I5d84dbea52595e61df56a5ff779d5e0ee0d84bdf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87248
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a DSD with the HotPlugSupportInD3, as when it RTD3, the device
will appear as not-present. This will cause Windows to constantly
try to enable it, causing an endless loop of the device becoming
visible.
Test=build and boot `starlabs/starlite_adl`, check CNVi is always
visible in device manager.
Change-Id: I598ab173074522e9d5af002782c5d3ec7691a815
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87325
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a DSD with the HotPlugSupportInD3, as when it RTD3, the device
will appear as not-present. This will cause Windows to constantly
try to enable it, causing an endless loop of the device becoming
visible.
Test=build and boot `starlabs/starlite_adl`, check Bluetooth is
always visible in device manager.
Change-Id: I51a2c764ebe8b98b137eb0c98cfdcf2de6f4b86c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87324
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The previous implementation used _PS0 and _PS3 methods to control the
device power states. These are now replaced by a _S0W object to better
align with both coreboot's existing RTD3 driver, and the examples in
the ACPI specification.
This ensures that the Bluetooth device is recognized as capable of
reaching D3Hot when the system is in S0.
Test=build and boot starlite_adl with Windows and Linux, check Bluetooth
is functional and power draw decreases ~0.4W with no devices connected.
Change-Id: I8aa49ee2220ba2ea39b343ea9a9486fca9f5f3d5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87241
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a check in the _ON method, similar to coreboot's ONSK handling
in its RTD3 driver, to determine whether the enable GPIO is already
asserted.
This prevents the OS from repeatedly invoking _ON, which can happen
because USB Bluetooth takes around 200ms to initialize after the
GPIO is enabled.
Change-Id: I424bc5f4c5b990fd5cb54daa3d6207828386c6f2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87239
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Guarding the existence of this register isn't necessary since we
guard its usage as well, and it complicates some subsequent changes,
so drop it.
Change-Id: I557c400e6dffeb9dc5b4b67a6cc6f15ba0ef27d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87343
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Update SoundWire driver to support ALC712 audio codec.
reference datasheet: Realtek ALC712-VB-CG Rev. 0.24
BUG=b:378629979
TEST=emerge-fatcat coreboot
A sound can be heard from the speaker,
the test instructions are as follows:
amixer -c 0 cset name='rt712 OT23 L Switch' on
amixer -c 0 cset name=''rt712 OT23 R Switch' on
amixer -c 0 cset name='rt1320-1 OT23 L Switch' on
amixer -c 0 cset name='rt1320-1 OT23 R Switch' on
amixer -c 0 cset name='Speaker Switch' on
speaker-test -D hw:0,2 -c 2 -t sine -f 440
Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
This change addresses an issue in the touch driver where the ACPI _PRW
method was added unconditionally. The ACPI _PRW method should only be
generated when an Interrupt() resource is used in the _CRS method.
When a GpioInt() resource is used instead, the _PRW method is not
required.
The ACPI generation code has been updated to conditionally add the
_PRW method based on whether the wake source is a GPIO interrupt or
an IRQ interrupt. Now, the _PRW method is only added when an IRQ pin
is specified, which is consistent with ACPI requirements.
BUG=none
TEST=Configure the DRIVERS_INTEL_TOUCH option on a motherboard that
has the necessary touch configurations with wake support. Verify that
the THC ACPI tables are correctly generated in the SSDT. If wake_gpio
(i.e. GpioInt()) is used for wake, no _PRW is generated for the device.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87085
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement logo bitmap rotation within fsp_convert_bmp_to_gop_blt() to
support devices with portrait-oriented displays. The rotation is driven
by the panel framebuffer orientation, allowing the logo to be displayed
correctly regardless of physical panel orientation.
This resolves issues where the logo was displayed incorrectly on
portrait-oriented displays.
Additionally, discard the display orientation change if the LID is
closed aka built-in display is not active. This will ensure that
display orientation is proper when extended display is attached w/o
any display rotation.
BUG=b:396580135
TEST=Verified BMP logo display in landscape mode on a portrait panel
with rotation enabled. Also verified portrait logo display in landscape
mode with rotation enabled.
Change-Id: I110bd67331f01e523c227e1a4bdb0484f0157a60
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86850
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Taken from an ACPI dump from a Windows JSL device with MIPI camera.
Change-Id: Ibdb2b148ebfa85c3d4f5af2594b9b8847215e726
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This patch corrects spacing around assignment operators in the
`fill_blt_buffer` to comply with coding style guidelines, specifically
within the BMP color translation logic for 1/4/8/24/32-bit images.
Change-Id: Ia243d11568ec4c3d1108ff60289743919394aa32
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86860
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a driver for the Intel Touch Controller (THC),
which supports HID-over-I2C and HID-over-SPI protocols, as well as
touch devices. The driver generates ACPI objects and publishes data
into the Secondary System Descriptor Table (SSDT) to facilitate
interaction with the touch hardware.
The driver implementation covers the following ACPI objects:
- _DSM (Device Specific Method)
- _CRS (Current Resource Settings)
- _STA (Power resource with Status), including _ON and _OFF methods
- _DSD (Device Specific Data) for THC-I2C
- _RST (Device Reset) for THC-SPI
Template device configuration for the following supported devices:
- Wacom: SPI touchscreen only
- Elan: both SPI and I2C touchscreen
- Hynitron: I2C touchpad only
It also includes template configurations for supported devices such as
Wacom (SPI touchscreen), Elan (SPI and I2C touchscreen), and Hynitron
(I2C touchpad). These configurations are divided into device-specific,
SoC-specific, and motherboard (MB)-specific details.
For SoC-specific configuration, the driver implements functions like
`soc_get_thc_hidi2c_info` and `soc_get_thc_hidspi_info`, which should
be defined in the SoC's `chip.c` file. Device-specific configurations
are provided by the driver for supported devices. For unsupported or
generic devices, the required information is expected to be provided
via the device tree. MB-specific information, such as LTR (Latency
Tolerance Reporting) values and speed, must be provided in the device
tree.
BUG=none
TEST=Configure the DRIVERS_INTEL_TOUCH option on a motherboard that has
the necessary touch configurations. Verify that the THC ACPI tables are
correctly generated in the SSDT.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ibcd2a75a41460dee67aebdc61ee9e85fa98b71bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop duplicate/unused `mclk` field, which corrects the size of the SSDB
struct to 108 bytes. Size/fields confirmed by comparing to DSDT
dumps of UEFI firmware and SSDB struct in linux MIPI driver (ref:
/include/media/ipu-bridge.h).
Change-Id: Iea5b2138d2396e32bcecb3a48ab2b159a9b33345
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add more platform type values. Values sourced from Slimbootloader and
various DSDT dumps on github.
Change-Id: If7ea46aad76dfedf89f764e60d9bf6061f53cbe1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86794
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The _STA method of drivers/i2c/generic PowerResource currently always
returns true. To allow generating _STA that returns the device's actual
power state, this CL adds a new boolean option `use_gpio_for_status` to
the `drivers_i2c_generic_config` struct, and propagates the value to
`acpi_power_res_params` to reuse the feature implemented for acpi/device
in [1].
[1] https://review.coreboot.org/c/coreboot/+/55027
BUG=b:397355818
TEST=Dump SSDT on redrix with CB:86749
Change-Id: I5c0a423730788d634a780d1d1d8c87a7007cc150
Signed-off-by: Momoko Hattori <momohatt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
This patch moves the debug print which prints the mapping between CPU
Type-C port and EC Type-C port from SoC code to generic driver code.
BUG=b:399032094
TEST=Check the Type-C port and EC port mapping in coreboot log
Change-Id: Iaef5813cc825569a53feba975258f7d5fadecfab
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86704
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds the parameter which allows for custom port mapping
between CPU Type-C port and EC Type-C port to accommodate the
non-sequential mapping. Mainboard code must configure this parameter
if the CPU Type-C port to EC Type-C port mapping is not sequential.
BUG=b:399032094
TEST=build and verify TCSS port and EC port mapping
Change-Id: Id92f942e5c6b27342777b3e6fd12aff264ccec1b
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch refactors low-battery user notification logic (Kconfig,
APIs to check if low-battery rendering is required, low-battery
shutdown is required) outside FSP driver code to ensure in future
non-FSP platforms might still be able to leverage this feature/logics
to render the low-battery indicator icon during boot.
Specifically, it:
- Moves Kconfig options related to low-battery notifications from
drivers/intel/fsp to lib/
- Relocates the low-battery check and shutdown APIs drivers/intel/fsp
to bootsplash.h
* Adjusts the vendor driver to utilize the new APIs for low-battery
rendering decisions.
* Drop the unwanted header file "fsp/api.h" from bmp_logo.c
This change avoids tight coupling of low-battery functionality to FSP,
promoting code reusability across platforms.
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: Iaa730dac2bb4866183408b6390221f0bb8411a48
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit relocates the BMP_LOGO related Kconfig options from the
FSP1.1 and FSP2.0 drivers to the common library (lib/).
This change:
- Centralizes the BMP_LOGO configuration, making it accessible to
all drivers and platforms.
- Removes duplicate Kconfig entries from the FSP drivers.
- Prepares for future refactoring where BMP_LOGO will be handled
entirely within the library, enabling its use by both FSP and
non-FSP platforms.
The following Kconfig options are moved under "Boot Logo Configuration"
menu option:
- `BMP_LOGO`
- `BMP_LOGO_COMPRESS_LZMA`
- `BMP_LOGO_COMPRESS_LZ4`
- `BMP_LOGO_FILE_NAME`
- `HAVE_BMP_LOGO_COMPRESS_LZMA`
- `HAVE_CUSTOM_BMP_LOGO`
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: I9bbfade9b919cfbd0b689a67c988ed8c65deb597
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86730
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit standardizes the Kconfig option for the boot logo file name
across FSP drivers and the common library.
The `FSP1_1_LOGO_FILE_NAME` and `FSP2_0_LOGO_FILE_NAME` options are
renamed to `BMP_LOGO_FILE_NAME`.
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: I6a6c2c6d235ad9643879b00232930c8a0d2e3801
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This change eliminates the HAVE_FSP_LOGO_SUPPORT Kconfig option.
It was initially used to control BMP_LOGO selection within the FSP2.0
driver. However, upcoming refactoring will move BMP_LOGO and its
implementation to the `lib` directory therefore, BMP_LOGO can be
used by both FSP and non-FSP SoC platforms.
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: I899bbfcf7e747abe69ff0866c4594a42278891b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86719
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
As mentioned in comments on CB:83422, size of the current data
block (which is also the last block of a capsule) was incorrectly used
in place of the capsule size:
- when publishing a capsule in CBMEM (this worked in practice because
CapsuleApp.efi allocates a continuous physical memory)
- when aligning target address (which could move output pointer past
previously allocated buffer by up to 7 bytes per capsule block)
Change-Id: I97a528e2611fcd711c555d0f01e9aadcd2031217
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84542
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As was pointed out in comments on CB:83422 [0], the code lacks overflow
checks:
- when computing size of capsules in a single capsule block
- when computing size of capsules in all capsule blocks
If an overflow is triggered, the code might allocate a capsule buffer
smaller than the data that's going to be written to it leading to
overwriting memory after the buffer.
[0]: https://review.coreboot.org/c/coreboot/+/83422
Change-Id: I43d17d77197fc2cbd721d47941101551603c352a
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84541
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PS0 and PS3 methods that return the Bluetooth power
resource. This allows the OS to turn on or off the device.
This fixes and issue where the Bluetooth reported a power
failure in device manager.
Change-Id: I0e37fc0369b1dc2b166f851daa183b145a09eb32
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86507
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
_PR3 should return resources required for the device to be in D3Hot
for which the Intel Bluetooth needs none, so remove it.
Change-Id: I65f206899affd46d791c2ba39235a1af320395d2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86595
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
