Program eMMC DLL settings for mc_apl1 mainboard, after that system can
boot up with eMMC successfully.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ife34e1b5079eca8e51f2270439dbe05d613ed688
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c7ccb6b29f
Original-Change-Id: I3d60f66ec5c7e09540ccda59f244aac6f78bf954
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19712
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/508771
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The mainboard siemens/mc_apl1 uses an external I/O port for console
output. For this reason we need to activate the 8250 LPC UART.
BUG=none
BRANCH=none
TEST=none
Change-Id: I32e68e06a64308bf56010ce2e8e48ba42fd788b2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ae10ec6239
Original-Change-Id: Ib5616a116aec6135191bdce95f9f9566ce13d6f1
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19694
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508770
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This device is no longer directly connected to the SOC so it
does not need to be enabled in coreboot.
BUG=b:35648259
TEST=build and boot on Eve
Change-Id: I5c13d993a2f37a023208fba2b745b70e9db9e310
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: c5eab98e78
Original-Change-Id: I4ed5a5575ce51ba5f6f48b54fab42e00134ea351
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19728
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/507638
The touchpad frequency was still slightly above 400kHz so tweak
the timing values manually to get under the spec limit.
BUG=b:35583133
TEST=verified the bus frequency with a scope to be < 400kHz
Change-Id: I07b171ebe912bf603049656e48beeeabdd56fef6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 4f7d536ed3
Original-Change-Id: I8bd071a8e15a791b7551ac256797e87abd6b5e5a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19727
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/507637
BUG=none
BRANCH=none
TEST=none
Change-Id: I7488d471b8e4c4a5fb8ea79302a1b39eee1e3333
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bddf86a259
Original-Change-Id: I5fcc83328441ccfb34ee63a7406d26e393633c21
Original-Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19685
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/506198
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I01428c56e7e416f191c07278e1241ef43e7a5d9f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2a59a44416
Original-Change-Id: I0eff29b74d7df331dcbf2c25799eaae4911e54fc
Original-Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/13749
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/506223
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Start-point is Gigabyte GA-G41M-ES2L.
This board features a G41 northbridge and an ICH7 southbridge. This
board has slots for both DDR2 and DDR3 (cannot run concurrently
though) but only DDR2 is implemented in coreboot. The SPI flash
resides in a DIP-8 socket.
Tested and working:
* DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky
with assymetric dimm setups);
* 3,5" IDE;
* SATA;
* PCIe x16 (with some patches up for review);
* Uart, PS2 Keyboard;
* USB, ethernet, audio;
* Native graphic init;
* Fan control;
* Reboot, poweroff, S3 resume;
* Flashrom (vendor and coreboot).
Tested but fails:
* DDR3 (not implemented in coreboot).
Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ieae7f68cadd2f41d94979c67267620272ed91319
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7d46e96ed7
Original-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18993
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506220
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This board features a PATA port.
TESTED PATA drive works in SeaBIOS and OS.
BUG=none
BRANCH=none
TEST=none
Change-Id: I139e711a715782032c8eecb7f983aecd991c15b7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dd2e35edc1
Original-Change-Id: I74dc72c22e6c4fed07f28ef7d88adde54656ae39
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19627
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506218
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This change is needed to minimize circuit level stress, by adjusting
circuit voltage for proper operation.
For mem config GPIO changes:
To avoid leakge as those pins have internal 20K pull and 3.3K pull down
on mainboard, change internal pull up to none.
BUG=b:37998248
TEST=Boot up into OS and enter s0ix.
Change-Id: I65b001b851b9cec3cf6cbbc0d345127f57912dd8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 55cad16ca5
Original-Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488
Original-Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19577
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/506217
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Move drivers/storage into commonlib/storage to enable access by
libpayload and indirectly by payloads.
* Remove SD/MMC specific include files from include/device
* Remove files from drivers/storage
* Add SD/MMC specific include files to commonlib/include
* Add files to commonlib/storage
* Fix header file references
* Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver
* Add Kconfig source for commonlib/storage
* Rename *DEVICE* to *COMMONLIB*
* Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE*
TEST=Build and run on Galileo Gen2
Change-Id: Ic527b2b23ea9cbaf42bd9411af766db9c053f13d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 48dbc663d7
Original-Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19672
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506215
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Probe RAM to find its size instead of hardcoding 1024M.
Also properly export it to memory map.
BUG=none
BRANCH=none
TEST=none
Change-Id: I145291ef63afe8856e4a958f97853680f24af54d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7723133073
Original-Change-Id: Ib411f0a068bd247a9e0cd0a59689a3896921483e
Original-Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/13754
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/506213
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
APU2 exposes a LPC header which can be used
in conjunction with a LPC TPM module.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie1c9be5d1e51d4f9f6aa64603c754dd3001bfeb2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ca39df8195
Original-Change-Id: If9312370a5071ffbeb6d83888c75fa69a0c27819
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18523
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506208
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Remove overrides that set platform defaults or insane values.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7c8643a958ab7883392de59a82531312b4fcd58e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5f9fe7232a
Original-Change-Id: I11d1c7155bf1c7f9298f60638a6c2f3b128f3fe8
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19354
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://chromium-review.googlesource.com/506185
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This mainboard contains an external RTC chip RX6110 SA. Enable usage of
this chip and set some initialization values to device tree.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4a7eee24699c5f84bb11436281a7b3d37501ddb7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3c4ddab1d4
Original-Change-Id: I5aceb4401f0bb059ef893dfe7d157716c82e4a76
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19647
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/506184
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The EC doesn't support it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I889b8d0ef04dadc4c7695c14197adf014279ab68
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a5fcc2e427
Original-Change-Id: Id2964002406a5fcf992f0ffc3627e3f66a2bb13f
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19654
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/506182
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The thinkpad-acpi driver uses the UCMS (CMOS) ACPI method to control the
ThinkLight from the Operating System. This patch adds partial support for
that method, enough to enable or disable the ThinkLight:
echo on >/proc/acpi/ibm/light
echo off >/proc/acpi/ibm/light
With the original BIOS the UCMS method exposes a wide range of values
through a generic /proc/acpi/ibm/cmos interface. With the changes suggested
in this patch that interface is also exposed but only accepts the commands
to enable or disable the ThinkLight; all other commands are ignored.
This change would potentially benefit all currently supported Thinkpad
models, I only have an X201 available for tests though.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id1345b20413a0dfd9834527b2b20faad2dccc75c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f63fbdb63a
Original-Change-Id: I80285f6630b5830766d82e3ecd174c4a51aa9066
Original-Signed-off-by: Stefan Ott <stefan@ott.net>
Original-Reviewed-on: https://review.coreboot.org/19644
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/506181
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Currently only one board uses this northbridge in coreboot but some
patches are pending to add more.
BUG=none
BRANCH=none
TEST=none
Change-Id: I05077218d6e434d9c52a86cf53003959afca435b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 512a2d1c4f
Original-Change-Id: If035e442d1a23674667f46a07b44c4f2b81be48c
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19650
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506177
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I58e973e472aa54b20b373c3a795516b1485f87d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1dcb2ac199
Original-Change-Id: I2308b069b8f2c601254169bcb6a34442c537a311
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19649
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506176
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I81abfe539a145d88017047d36c36cf6c54b65ae0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c5fba2c17c
Original-Change-Id: I15550b1cc1a7ccfecba68a46ab2acaee820575b9
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19648
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506175
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
- set GPIO_183 to high level for enabling the power of SD card
- delete all GPIOs for JTAG interface because they lead to problems with
Lauterbach debug hardware
BUG=none
BRANCH=none
TEST=none
Change-Id: I684fc6815be9c49dc59ab326c491edd962c4f8a4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 4125dde2be
Original-Change-Id: I24bfff479601933c43e3dcbfa3baa49510831703
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19623
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/506173
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
s230u seems only have two sata ports: one for the 2.5in hdd and one for
msata. map 0x11 (port 0 & 4) enables hdd but not msata, and map 0x5
(port 0 & 2) enables both.
BUG=none
BRANCH=none
TEST=none
Change-Id: I11aba1d95e53ffc8e97c152bf6aa6b01d299820f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 72f730e23c
Original-Change-Id: I1e9e96f0d0849b1e8c4e02aa4f686ceb5e10b3ab
Original-Signed-off-by: Bill XIE <persmule@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19523
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/506170
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The coreboot had no supported the different frequency for gru yet.
e.g:
we can't support the bob to run ddr 800M for rev3 board and
run 928M for rev4 board.
So, in order to support the 800M and 928M ddr frequency for bob different
boards. We will use the ram_id and board_id to select the board on bob.
BRANCH=none
BUG=b:36666655
TEST=boot from bob, tested with memtester/s2r/reboot on bob.
Change-Id: I613050292a09ff56f4636d7af285075e32259ef4
Original-Change-Id: I613050292a09ff56f4636d7af285075e32259ef4
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19558
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/488421
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to
modulate the frequency of the Silicon Creations Fractional PLL in order
to reduce EMI.
We need to turn the DPLL spread spectrum feature on to
reduce the EMI noise for DDR on bob.
BRANCH=none
BUG=b:37262721
TEST=mem checks the register value on bob.
localhost / # mem r 0xff76004c ---> 0x00000100
localhost / # mem r 0xff760050 ---> 0x00000860
TEST=Tested with memtester/s2r/reboot on bob.
Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Original-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19557
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/377691
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Tested against a lenovo-manufactured tpm 1.2 module:
a /dev/tpm0 visible inside GNU/Linux, but there is no menu items in
SeaBIOS' interface, which seems a common issue of SeaBIOS on ivb boards.
BUG=none
BRANCH=none
TEST=none
Change-Id: I81485ce4f64e0e58a3204052a314cf20c6eaa439
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6dcb789da9
Original-Change-Id: Id0dee74d945bae5d77eb669d8b9d468a67aee508
Original-Signed-off-by: Bill XIE <persmule@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19521
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/501164
This replaces the custom environment controller handling in the it8728
driver with the common library.
It also updates the two existing boards with hwm register settings in
their devicetree config so they better match their vendor BIOS fan
control settings.
BUG=none
BRANCH=none
TEST=none
Change-Id: I200629a1d69e39ba9b5f7fdb9801fc4df5c320e5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1f064d7551
Original-Change-Id: Idf0c8908ba5ad6ff552b8302bffc638aa9052941
Original-Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Reviewed-on: https://review.coreboot.org/19293
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/501163
BUG=None
TEST=emerge-sand coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I9b70609a74d70856fc3aa72250f9ff1bc240af0b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 709bc6eada
Original-Change-Id: I86a35551a9348ff6ad26dfccd3b2786282d56069
Original-Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/19479
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/501158
Configure the SD controller to handle the SD card slot.
* Galileo supports a removable SD card slot.
* Set SD card initialization frequency to 100 MHz.
* Set default removable delays.
* Build SD/MMC components by default
TEST=Build and run on Galileo Gen2
Change-Id: Icb6ca60d4f7ca9e7f6b387c622f7417713a2f9c7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1ea7cce8ae
Original-Change-Id: Iaf4faa40fe01eca98abffa2681f61fd8e059f0c4
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19212
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/501152
This reverts commit 952d9af2ed.
I need to do an Eve BIOS release and this cannot be present yet as it
has to be released at the same time as the new touchpad firmware.
BUG=b:35581264
BRANCH=none
TEST=none
Change-Id: I35da873b5f071e803688ff8ccf08274303b8f228
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/498587
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This patch adds the eMMC as one of the thermal sensor under DPTF.
Also, updates few comments for better interpretation and mapping.
BUG=None
BRANCH=None
TEST=Built for poppy.
Change-Id: I22edad5afd0e24fd19ee7857b750f0168d13a818
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c9026b2945
Original-Change-Id: I6d05bb7a2f857dc5bc98227c8327b2ff1bd5b913
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19524
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/498308
Update the DPTF parameters based on thermal test result.
1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
CPU passive point:83, critial point:99
TSR0 passive point:60, critial point:70
TSR1 passive point:50, critial point:90
TSR2 passive point:77, critial point:90
2. Update PL1/PL2 Min Power Limit/Max Power Limit
Set PL1 min to 4W, max to 12W, and step size to 0.2W
3. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 5secs
Change CPU Effect on Temp Sensor 0 sample rate to 60secs
The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs
Change Charger Effect on Temp Sensor 2 sample rate to 30secs
Change CPU Effect on Temp Sensor 2 sample rate to 120secs
BUG=None
TEST=build and boot on electro dut
Change-Id: I4488a6d4abbf90f34e5f7174ab71a6e62c5cb996
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8caf8a23f9
Original-Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db
Original-Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/19538
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/498307
Turn on device 1c.0 in order to enable devices
under it.
BUG=b:37486021, b:35775024
BRANCH=None
TEST=Boot from NVMe
Change-Id: I87c1f0a96067ec92f3df623f5327be243d53171f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f49785e8e2
Original-Change-Id: Ide66823283c58d2bea0c9886f762f0581741affe
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19533
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/497403
This is required to ensure that SCI is generated whenever a host event
is set for MODE_CHANGE. Thus, when wake from MODE_CHANGE event occurs,
eSPI SCI is generated which results in kernel handler reading host
event from the EC and thus causes the wake pin to be de-asserted.
BUG=b:37223093
TEST=Verified that wake from mode change event works fine in suspend
mode and there is no interrupt storm for GPE SCI after resume.
Change-Id: Ib82e9291b55c68a4508bd1ce3f5f5ad08fdb228e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 730fc6c7d8
Original-Change-Id: I1dd158ea0e302d5be9bcaa531cd1851082ba59fd
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19559
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/497399
soc/i2c.h does not need to be included in this compilation unit.
BUG=none
BRANCH=none
TEST=none
Change-Id: I57bb42eb4565e9bf2faf7bce34b1115524e913dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c2b1390d47
Original-Change-Id: Ife11642d2e69af7235c93fc54bba38853b046169
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19572
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/497398
Currently native video init works on port HDMI1 (wired to the
on-board DVI-D socket) , HDMI3 (the on-board HDMI port), and the VGA
port, both text mode and fb mode.
Every ports works on GNU/Linux.
Tested against an IVB cpu (i7-3770T).
BUG=none
BRANCH=none
TEST=none
Change-Id: I637c593db52f54f044eb644dea0054c406e17c0a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91fbb25ec7
Original-Change-Id: If00a7247df0c32b3d1f489fb92d86baaa8fdf8ba
Original-Signed-off-by: Bill XIE <persmule@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19522
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/497395
Add some known good values for some thinkpads displays.
Known good means that at this pwm frequency the display is evenly lit
on all duty cycles, the display makes minimal to no noise at lower
duty cycles and the display does not flicker. This values differs from
vendor (which uses an obviously wrong display clock (190MHz instead
of 320MHz) resulting in frequency more than 60% off the intended
value.
TESTED on Thinkpad X200 with edid ascii string in list and removed
from list to see if notice message is shown.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6df100df0f80ce479ace6ee2c1d59114c17f1a7a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 20cb85fa98
Original-Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19500
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/496055
Remove the code that was enabling the keyboard backlight at boot
since this is not desired behavior for this device.
BUG=b:35581264
TEST=build and boot on Eve and ensure keyboard backlight does
not turn on when booting but can still be enabled in the OS.
Change-Id: Ifd608411b96d39894bec44084803011d910b9543
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ec10c9a11c
Original-Change-Id: I7229cf962597c0de74dc005f7afb9408f7a66f42
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19550
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/496050
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Set GPP_A13/SUSWARN# pin mode to native function 1. This pin is tied
to SUSACK# in the schematic and and is intented to be used in Deep Sx
so it should not be configured for GPIO mode.
BUG=b:35581264
TEST=build and boot on Eve platform, test that Deep S3 and Deep S5
are still functional. (this change should have no visible effect)
Change-Id: I66e41615c4a19083b8bc5835f1139e8f15cd372b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1a51086815
Original-Change-Id: Ie2dc24d095872ab93a5bfcbe5307c3b7a8e4dbcc
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19549
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/496049
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Kevin's center logic isn't super clean so it needs 925 mV for center
logic. All newer gru variants only need 900 mV.
BRANCH=gru
BUG=b:37429075
TEST=Reboot tests
Change-Id: I8c3bd6c245700b23c27cd5758c35c9993f801cb4
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/479463
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19357
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480971
Reviewed-by: Julius Werner <jwerner@chromium.org>
Board Scarlet doesn't use usbphy1.
BUG=b:37685249
BRANCH=gru
TEST=boot Scarlet, check the firmware log, and confirm
no errors about USB1
Original-Change-Id: I66e0d8a235cc9057964f7abca32bc692d41e88fd
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/19489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3b62ea72c1db33fe8eb6386be38989f223d85039
Reviewed-on: https://chromium-review.googlesource.com/494906
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
1. Add support for using cr50 I2C TPM on poppy. This will not be
enabled until the next build.
2. Also, configure GPIOs for SPI and I2C TPM only if the corresponding
Kconfig options are set.
BUG=b:36265511
TEST=Verified on a reworked board that I2C TPM communication works
fine.
Change-Id: I570504113c8da06d5834a3d80a10353d1e41fdfa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 553f7fb27c
Original-Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19518
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/494608
The AFCAdditional Flash Control Register is set by
southbridge code.
Remove redundant calls and get rid of it in autoport.
BUG=none
BRANCH=none
TEST=none
Change-Id: I912dc6f185b7df5e1b54aa90e64d7cfdb0bc0d63
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0a4a4f7ae4
Original-Change-Id: I627082e09dd055e3b3c4dd8e0b90965a9fcb4342
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19493
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/493981
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Based on Thinkpad x230 and schematics.
Verified by autoport.
USB debug port is the left front usb port
Thanks to Holger Levsen for the device.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iec695049d8bf2e115011b513af3d4eebe5b433a0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: db508565d2
Original-Change-Id: I97c8e01a3ce0577d7dc9e8df7d33db3b155fe3d6
Original-Tested-on: lenovo x1 carbon gen 1
Original-Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Original-Reviewed-on: https://review.coreboot.org/16994
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/493980
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Haswell, Broadwell, Baytrail, and Braswell ChromeOS devices'
FADT version were incorrectly set to 3, rather than the correct
ACPI_FADT_REV_ACPI_3_0. The incorrect value resulted in these
devices reporting compliance to ACPI 2.0, rather than ACPI 3.0.
This mirrors similar recent changes to SKL and APL SoCs.
Test: boot any affected device and check ACPI version reported
vai FADT header using OS-appropriate tools.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia974300bdc555a1062d2779083a19c3838f6cf78
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7ee81a4a01
Original-Change-Id: I689d2f848f4b8e5750742ea07f31162ee36ff64d
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19498
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/493979
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Enable audio:
* Add verb table for ALC286 & ALC298
* Enable virtual channel 1 for DmiVc1 & HdaVc1.
TEST= Build for kblrvp3 as well as kblrvp7. Boot to OS & verified
working of audio on both the boards.
Change-Id: I4f8dac51437704e61bf31ecb6f94224a1a4bf6f1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: af295495c2
Original-Change-Id: Id27e3cf585b93ed4131d7bf3d3b53d3f5404b18e
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18875
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/493976
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
