UPSTREAM: mainboard/pcengines/apu2: Add LPC TPM support

APU2 exposes a LPC header which can be used
in conjunction with a LPC TPM module.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ie1c9be5d1e51d4f9f6aa64603c754dd3001bfeb2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ca39df8195
Original-Change-Id: If9312370a5071ffbeb6d83888c75fa69a0c27819
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18523
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506208
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>

src/mainboard/pcengines/apu2/Kconfig

@@ -28,6 +28,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_8192
 	select HUDSON_DISABLE_IMC
 	select USE_BLOBS
+	select TPM
+	select MAINBOARD_HAS_LPC_TPM
 
 config MAINBOARD_DIR
 	string

src/mainboard/pcengines/apu2/devicetree.cb

@@ -73,7 +73,10 @@ chip northbridge/amd/pi/00730F01/root_complex
 						device pnp 2e.607 off end
 						device pnp 2e.e off end
 					end # SIO NCT5104D
-					end # LPC 0x439d
+					chip drivers/pc80/tpm
+						device pnp 0c31.0 on end
+					end # LPC TPM
+				end # LPC 0x439d
 
 				device pci 14.7 on  end # SD
 				device pci 16.0 on  end # USB EHCI2 usb[8:7] - muxed with XHCI

src/mainboard/pcengines/apu2/romstage.c

@@ -31,6 +31,8 @@
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 #include <Fch/Fch.h>
+#include <tpm.h>
+
 #include "gpio_ftns.h"
 
 static void early_lpc_init(void);
@@ -92,6 +94,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	*/
 	disable_cache_as_ram();
 
+	init_tpm(false);
+
 	outb(0xEA, 0xCD6);
 	outb(0x1, 0xcd7);