Currently, the USB ports are still powered during S3, so turning
them off may reduce the power consumption.
Note that, when the USB Always on feature is enabled, the USB
ports are always powered, regardless of the USBP state.
This patch also disables the audio, as it might consume some
power or generate some noise.
Both the USB power and the audio are reenabled by coreboot during
the poweron.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iab4aff2c38ee494a5db3b0804f154ecbd4955f75
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 435d307415
Original-Change-Id: If0431b1315fffef2e372e7023f830a66bb7fddae
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18464
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/449818
This timeout is probably needed on all devices with Lenovo H8 embedded
controllers so set the default there.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8c622291d18ebe5433d10f839abb76dfbf92fead
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f77d6ba911
Original-Change-Id: I830ab1894f7c0f10f55c82e398becf44d810852d
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18274
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/449815
RAMD_ID_1 moves to PAD_DSI_TE and RAM_ID_2 moves to PAD_RDP1_A on Rowan.
BUG=chrome-os-partner:62672
BRANCH=none
TEST=emerge-rowan coreboot
Change-Id: I64fd29de607a0b360d355fd3724e3a649adc658b
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/448397
Reviewed-by: Julius Werner <jwerner@chromium.org>
The differential signal of DQS need keep low
level before gate training. RPULL will connect
4Kn from PADP to VSS and a 4Kn from PADN to
VDDQ to ensure it.But if it have PHY side ODT
connect at this time,it will change the DQS
signal level.So it need disable PHY side ODT
when do gate training.
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/448278
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Gru/Kevin use the 933M(actually 928M for better jitter) as max sdram freq,
while bob would use 800M.
It's normal some variants can't meet 928M SI requirement and hence want
use a lower freq as spec.
BUG=chrome-os-partner:61001
BRANCH=gru
TEST=check dpll is 800M on bob
Change-Id: I46afba8d091f1489feeb20cafc44decaa81601fc
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/420208
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Shasha Zhao <Sarah_Zhao@asus.com>
Tested-by: Shasha Zhao <Sarah_Zhao@asus.com>
(cherry picked from commit eba5dff79eeedae5ff608d2d8d297ccf9c13cb55)
Reviewed-on: https://chromium-review.googlesource.com/448277
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
The cr50 part on reef is connected to the SoC's UART lines. However,
when the tx signal is low it causes an interrupt to fire on cr50.
Therefore, keep the tx signal high in suspend state so that it doesn't
cause an interrupt storm on cr50 which prevents cr50 from sleeping.
BUG=chrome-os-partner:63283
BRANCH=reef
TEST=s0ix no longer causes interrupt storm on cr50. Power consumption
normal.
Change-Id: I38a14abff2f619b2b11a8f3a12ce54f61028fb48
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6295b8a57a
Original-Change-Id: Idaeb8e4427c1cec651122de76a43daa15dc54d0f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18491
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446843
Apply tuning for the PCH I2C buses on Eve based on rise/fall time
measurements that were done with a scope.
BUG=chrome-os-partner:59686
BRANCH=none
TEST=Manual testing on Eve P1 to verify that all devices on I2C
buses are still functional. Post-tuning measurement will be done
once a new firmware is released.
Change-Id: If6d7f8c77504c281bc4c0788ec0c5aa5c2607ed2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d4d6ba180d
Original-Change-Id: I3d70ff455a20ecda374d7e7fa6cd3ab15e7f2621
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18487
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446842
This patch tries to clean the code by:
o removing duplication of LPC GPIO pads
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
Also adds vital defaults in Kconfig so it is possible to build an image.
BUG=none
BRANCH=none
TEST=none
Change-Id: I31e2bda3b511f14fc46493f2d669b26a0329082d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a489237d5
Original-Change-Id: Id9913f3b053189166392271152ce5300d82a7de8
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18479
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/446841
BUG=chrome-os-partner:62967
BRANCH=None
TEST=Verified that touchscreen works on power-on and after
suspend-resume as well.
Change-Id: If0956204a6c6c266ea2383e29d8738b282caeb2e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 613350897d
Original-Change-Id: Id674cbcc2d524a6ed2883bf9f0e9e076890f9a85
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18466
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446839
Follow up to https://review.coreboot.org/#/c/18460/
BUG=none
BRANCH=none
TEST=none
Change-Id: I829c8546ac8d9883d973ff860986389d67b620c6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 96af0afcd7
Original-Change-Id: Ic3aada2acf3051622698e10d2e764050e16480d5
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18475
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446387
This patch adds the DPTF settings specfic to the mainboard and enables
the CPU and other thermal sensors as participant device for poppy.
It enables the DPTF flag in the device tree for poppy. It also includes
the DPTF specific ASL file in the main DSDT definition.
BUG=None
BRANCH=None
TEST=Built for poppy.
Change-Id: I840b6d9fa170718b309c6a57c8d88e272bf92df5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d56fae18dc
Original-Change-Id: If44b01dd3c17fea06681ccf50e8e9f406e642e36
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/17926
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446386
Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
minnow3 doesn't build right now due to API divergence on master branch.
Follow up with recent changes.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib193ed00b806294dc9210b566d7617aab6861190
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a5c029f235
Original-Change-Id: Iee84750292f22aa040127bcbfe523a0b9eaa8176
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18476
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/446384
These parameters are probably the result of copying from the Thinkpad
X60 code.
BUG=none
BRANCH=none
TEST=none
Change-Id: I91aec0b2ccdafc1134183ad897c3123b2095fcdd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00954f0815
Original-Change-Id: I29763b38618d4b306c37424c5c4b57dfcf69424b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18290
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/446757
Set the proper memory configuration for the MinnowBoard 3. The current
values are copied from intel/leafhill. Set the proper values for
MinnowBoard 3.
BUG=none
BRANCH=none
TEST=none
Change-Id: I422eda191c564e04331665413074b016175153ed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97f542efc2
Original-Change-Id: Ie37842f5ce2cabaa892f42ee945c91fe3ace527a
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18374
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/445835
This commit adds the initial scaffolding for the MinnowBoard 3
with Apollo Lake silicon.
This mainboard is based on Intel's Leafhill CRB with Apollo Lake
silicon. In a first step, it concerns only a copy of intel/leafhill
directory with name changes. Special adaptations for MinnowBoard 3
mainboard will follow in separate commits.
BUG=none
BRANCH=none
TEST=none
Change-Id: I266e9f12db1c4824545871e6a0d1ac89f8d8255f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 35f03d9027
Original-Change-Id: I7563fe37c89511c7035c5bffc9b034b379cfcaf4
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18298
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445834
There was a 'typo' where the subsystem id was set instead of the codec
vendor id. This caused the lynxpoint HDA codecs init to fail to find
the proper codecid verbs so codecs were never initialized. That caused
the headphones jack to not work.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6821c13910c1cd8c91ae6a70e15a222372b135dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 02756b8ffb
Original-Change-Id: I975031643fc42937ecaea2300639b90632543f67
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/18411
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/445829
The M.2 SSD is on the SATA port 3, which also required the DTLE setting
to be set.
This fixes issues with the M.2 SSD not being detected/stable.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6922d284aeb07f2e32ced1cffaa47fcc1fd28637
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a462c157f8
Original-Change-Id: Id39d9ec395a2d9d32be4c079678d0708f08b3935
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/18409
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445827
The K4B4G1646E-BYK0 shares sdram config with K4B4G1646D-BYK0.
For clarity, sdram-ddr3-samsung-2GB now is used by
- K4B4G1646D-BYK0
- K4B4G1646E-BYK0
- K4B4G1646Q-HYK0
BUG=chrome-os-partner:62131
BRANCH=veyron
TEST=emerge
Change-Id: I461c6f36c28ea0eeaf7d64292c9c87ab0c9de443
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/446197
Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit f98251a4a4)
Reviewed-on: https://chromium-review.googlesource.com/446300
This adds SDRAM entries for the following modules:
- Micron: DDMT52L256M64D2PP-107
- Hynix: H9CCNNNBKTALBR-NUD
They are compatible with Samsung K4E8E324EB-EGCF, so this just
copies sdram-lpddr3-samsung-2GB-24EB.inc and changes the name used
in the comment near the top.
Notes on our "special snowflake" boards:
- veyron_danger's RAM ID is hard-coded to zero, so I skipped changes
involving the binary first numbering scheme.
- Rialto's SDRAM mapping is different, so I padded its SDRAM entries
to 24 to match other boards.
- veyron_mickey requires different MR3 and ODT settings than other
boards due to its unique PCB (chrome-os-partner:43626).
BUG=chrome-os-partner:59997
BRANCH=none
TEST=Booted new modules on Mickey (see BUG)
Change-Id: I22386a25b965a4b96194d053b97e3269dbdea8c7
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/412328
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Jiazi Yang <Tomato_Yang@asus.com>
Tested-by: Jiazi Yang <Tomato_Yang@asus.com>
(cherry picked from commit bd5aa1a548)
Reviewed-on: https://chromium-review.googlesource.com/446299
Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This is done to avoid any conflicts with same IRQ enums defined by other
drivers.
BUG=None
BRANCH=None
TEST=Compiles successfully
Change-Id: I54701329455709ce023bf363bdacdadf4f7d2639
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5b9b593f2f
Original-Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18444
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446382
poppy board uses Maxim 98927 speaker codec and Realtek RT5663
for headset. Select the apropriate NHLT blobs to be packaged in CBFS.
Also, generate the required ACPI NHLT table for codec and the supported
topology in poppy.
BUG=chrome-os-partner:62051
BRANCH=None
TEST=With the required driver support in kernel verify that
the Audio plays on on-board speakers and headset, recording
works from on-board mics and headset mics.
Change-Id: I8134a6978c2e21ff0d167a4ee038a1bc69df591f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2f5446be4a
Original-Change-Id: I98c65038b35fe99a661807de0766e6eac2c80eed
Original-Signed-off-by: M Naveen <naveen.m@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18214
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445640
Add the audio devices to Eve mainboard:
- Describe Maxim 98927 speaker amps and RT5663 headphone codec
in ACPI so they can be enumerated by the OS.
- Supply NHLT binaries for MAX98927, RT5663, and DMIC_4CH.
BUG=chrome-os-partner:61009
TEST=manual testing on Eve P1 with updated kernel to ensure that
both speakers and headset are functional. DMIC support is
is still being worked on and is not yet functional.
Change-Id: Ib2965da2bb25c6d3b48d1da9aad2641b8eaf9189
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5492bfb55c
Original-Change-Id: I5243e35d159a0ed15c6004e94ba5a50b28cff0a9
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18398
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/445639
Update GPIO controls and mainboard configurations for Rowan.
BUG=chrome-os-partner:62672
BRANCH=none
TEST=emerge-rowan coreboot
Change-Id: I18ebc3ccf4c7d051839d7c50e9b0682ef8f09830
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/430557
Reviewed-by: Julius Werner <jwerner@chromium.org>
Wacom I2C driver does the same thing as I2C HID driver, other than
defining macros for Wacom HID. Instead of maintaining two separate
drivers providing the same functionality, update all wacom devices to
use generic I2C HID driver.
BUG=None
BRANCH=None
TEST=Verified that ACPI nodes for wacom devices are unchanged.
Change-Id: I40316a2bc0a1210661becf0bf392d259310adbc5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5360c7ef94
Original-Change-Id: Ibb3226d1f3934f5c3c5d98b939756775d11b792c
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18401
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445638
Enable Fast-Plus speed for the touchscreen device so it can
be used at 1MHz instead of 400KHz.
BUG=chrome-os-partner:61277
TEST=manual testing on Eve P1, needs backported kernel patches
to actually make use of any I2C speed other than 400KHz
Change-Id: I0bc6834ed731a60108a77bedef7816bd7bffcc20
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 658a6dc78d
Original-Change-Id: I3f44ff4a02a02a7b05e69ad54d4c6d60e5878393
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18397
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/445637
Since we are not using gpio regulators on reef anymore, remove the
selection from Kconfig as well.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Change-Id: Iaa6ef0c06a23d42c0d92a57a7b3bbf634c4d14d5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: abd5d1d35c
Original-Change-Id: Iae7d88dec3ac476d65b292f97a6ba3add71ce07a
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18399
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445139
Move code common code from each variant's mainboard.asl into
common ACPI code for all variants (like google/auron). This also
adds the _PRW method for the LID0 device for falco and peppy, which
omitted the function when they were originally upstreamed.
See Chromium commit c8b41f7, falco: Add _PRW for LID0 ACPI Device
BUG=none
BRANCH=none
TEST=none
Change-Id: I9199128d0270e1ed6f2600282216950a592001df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4b8252ed76
Original-Change-Id: I7f5129340249a986f5996af37c01ccbde8d374e8
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18368
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445136
Apply the measured rise and fall times for I2C bus 1 on Eve
so it can be tuned properly for 400KHz operation.
BUG=chrome-os-partner:63020
TEST=verify I2C1 bus speed with a scope
Change-Id: I4bd676d69f77cc8c90cf3c2eb6d29776039aee15
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c86fa6d975
Original-Change-Id: I32b5aa460ea35aadca7f3d52324a64880764919f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18396
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445135
Currently UART0 GPIOs are being put into native mode during FSP-S
stage, so have ramstage re-configure them back to regular GPIO mode.
GPP_C8 does not seem to be functioning properly when routed to the
APIC, possibly due to the UART0 being enabled even though it is unused,
which is required because UART0 is PCI 1e.0 and so must be present for
other 1e.x functions to be enumerated. Instead, use this pin as a GPIO
interrupt so it will be routed through the GPIO controller at IRQ 14.
GPP_C9 was inverted and was only working because the pin was being
re-configured in FSP-S.
Also export the reset gpio as a device property so it can be used by
the kernel driver, which will stop it from complaining at boot.
BUG=chrome-os-partner:61233
TEST=verify that the interrupt and device is functional in the OS
Change-Id: Idca8e787f9d99f2bba03f103ae6fcf0d49ad6a3f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6c8238521e
Original-Change-Id: Iaf9efbf50a13a981c6a9bbd507475777837e9c12
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18395
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445134
Created using autoport plus some manual work and copying from G505S to
account for the non-H8 EC.
This model uses the same ENE KB9012 EC as the G505S.
Tested:
- Mainboard variant with 8GB Elpida DDR3
- SeaBIOS payload
- Booting into Linux 4.9.6 with Debian/unstable installed on the
internal HDD/SDD slot
- Native raminit
- Both native VGA init and option rom VGA init
- Basic TPM functionality (auto-detection and RNG)
- Battery status readout
- Basic ACPI functions (power button event; power-off; reboot)
- thinkpad-acpi hotkey functions
- thinkpad-acpi LED control (red thinkpad LED)
- Suspend to RAM and resume works
- Mini displayport output works
Known issues:
- Patches needed for EC battery support
https://review.coreboot.org/#/c/18348/https://review.coreboot.org/#/c/18349/
- No thermal zone since temperature sensing is not H8-compatible
and needs to be reverse engineered.
Not tested:
- msata/wwan (probably works)
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifd82918d0eb93002027b9ed841e138419691c854
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cee930a39b
Original-Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Change-Id: I52bc4515277e5c18afbb14a80a9ac788049f485c
Original-Reviewed-on: https://review.coreboot.org/18351
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/445636
This mainboard uses two i210 Ethernet controller. Therfore we enable the
usage of the i210 driver and have to provide a function to search for a
valid MAC address for all i210 devices by using Siemens hwilib.
BUG=none
BRANCH=none
TEST=none
Change-Id: I70c71081b5a190304a2f36c4f185c9564822f0d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 480eab0da9
Original-Change-Id: I36246cdef987fcece15a297ebb2f41561fca1f69
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/18380
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/445155
The hybrid driver select by DRIVERS_LENOVO_HYBRID_GRAPHICS doesn't work
for t400/t500.
Replace it with a custom romstage implementation.
Tested on Lenovo T500 with dual graphics:
* Intel Native GFX init
* AMD VBios
* GNU Linux 4.8.13
* SeaBios as payload
* Discrete is working (44 W)
* Integrated is working (24 W)
* Switchable is working (34 W)
** Both GPUs are enabled, with Intel being connected to the panel
** DRI_PRIME allows to use AMD GPU
** ACPI doesn't seem to work (no vgaswitcheroo)
Depends on Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422
Depends on Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201
BUG=none
BRANCH=none
TEST=none
Change-Id: I8319fb3c52c32b548820f49dea0aee53b8e509d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f9d5308690
Original-Change-Id: I7496876e9b434d4a2388e1ede27ac604670339b7
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18010
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/445147
It rewrites the results of receive enable stored in the upper nvram
region, to avoid running receive enable again.
Some debug info is also printed about the self-refresh registers.
(Not enforcing a reset here, since 0 does not necessarily mean it's
not in self-refresh).
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie8a85069cc613706c1405e150bece11bc6ba43c1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ef7e98a2ac
Original-Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17998
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445144
Previously the raminit failed on hot reset and to work around this
issue it unconditionally did a cold reset.
This has the following issues:
* it's slow;
* when the OS issues a hot reset some disk drives expect their 5V
power supply to remain on, which gets cut off by a cold reset,
causing data corruption.
To fix this some steps in raminit must be ommited on the reset path.
This includes receive enable calibration.
To achieve this it stores receive enable results in RTC nvram for them
to be rewritten on the resume path.
Note: The same thing needs to be done on the S3 resume path.
Calling a hot reset after raminit "outb(0x6, 0cf9)" works.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7abad55524ecea8bbd828aba6dd3ce7708f1a7bd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97e13d84c3
Original-Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18009
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/445143
This commit makes a basic adjustment for GPIOs, device tree, flash map and
MRC settings. With these basic settings the mainboard boots into
Linux lubuntu 4.8.0-22-generic using SeaBIOS. More adjustments will follow.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic79be51b2d99ebbc2629e19f6110ad10f12028ab
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 6abdbcd4dc
Original-Change-Id: Ia920d236814f2e6a9b777dd1e4b4feef0ddf7721
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/18292
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/443925
