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UPSTREAM: intel/minnow3: Configure memory properly

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Set the proper memory configuration for the MinnowBoard 3.  The current
values are copied from intel/leafhill.  Set the proper values for
MinnowBoard 3.

BUG=none
BRANCH=none
TEST=none

Change-Id: I422eda191c564e04331665413074b016175153ed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97f542efc2
Original-Change-Id: Ie37842f5ce2cabaa892f42ee945c91fe3ace527a
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18374
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/445835
This commit is contained in:
Brenton Dong 2017-02-15 11:50:02 -07:00 • committed by chrome-bot
commit 6eda91a0ac
1 changed files with 5 additions and 5 deletions
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10
src/mainboard/intel/minnow3/romstage.c
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@ -61,7 +61,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
memupd->FspmConfig.InterleavedMode = 0x2;
memupd->FspmConfig.ChannelsSlicesEnable = 0x0;
memupd->FspmConfig.MinRefRate2xEnable = 0x0;
memupd->FspmConfig.DualRankSupportEnable = 0x1;
memupd->FspmConfig.DualRankSupportEnable = 0x0;
memupd->FspmConfig.RmtMode = 0x0;
memupd->FspmConfig.MemorySizeLimit = 0x1800;
memupd->FspmConfig.LowMemoryMaxValue = 0x0;
@ -69,7 +69,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
memupd->FspmConfig.HighMemoryMaxValue = 0x0;
memupd->FspmConfig.DIMM0SPDAddress = 0x0;
memupd->FspmConfig.DIMM1SPDAddress = 0x0;
memupd->FspmConfig.Ch0_RankEnable = 0x3;
memupd->FspmConfig.Ch0_RankEnable = 0x1;
memupd->FspmConfig.Ch0_DeviceWidth = 0x1;
memupd->FspmConfig.Ch0_DramDensity = 0x2;
memupd->FspmConfig.Ch0_Option = 0x3;
@ -77,7 +77,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
memupd->FspmConfig.Ch0_TristateClk1 = 0x0;
memupd->FspmConfig.Ch0_Mode2N = 0x0;
memupd->FspmConfig.Ch0_OdtLevels = 0x0;
memupd->FspmConfig.Ch1_RankEnable = 0x3;
memupd->FspmConfig.Ch1_RankEnable = 0x1;
memupd->FspmConfig.Ch1_DeviceWidth = 0x1;
memupd->FspmConfig.Ch1_DramDensity = 0x2;
memupd->FspmConfig.Ch1_Option = 0x3;
@ -85,7 +85,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
memupd->FspmConfig.Ch1_TristateClk1 = 0x0;
memupd->FspmConfig.Ch1_Mode2N = 0x0;
memupd->FspmConfig.Ch1_OdtLevels = 0x0;
memupd->FspmConfig.Ch2_RankEnable = 0x3;
memupd->FspmConfig.Ch2_RankEnable = 0x1;
memupd->FspmConfig.Ch2_DeviceWidth = 0x1;
memupd->FspmConfig.Ch2_DramDensity = 0x2;
memupd->FspmConfig.Ch2_Option = 0x3;
@ -93,7 +93,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
memupd->FspmConfig.Ch2_TristateClk1 = 0x0;
memupd->FspmConfig.Ch2_Mode2N = 0x0;
memupd->FspmConfig.Ch2_OdtLevels = 0x0;
memupd->FspmConfig.Ch3_RankEnable = 0x3;
memupd->FspmConfig.Ch3_RankEnable = 0x1;
memupd->FspmConfig.Ch3_DeviceWidth = 0x1;
memupd->FspmConfig.Ch3_DramDensity = 0x2;
memupd->FspmConfig.Ch3_Option = 0x3;