Add a new driver GOOG0006 to report tablet switch
to user space.
On glados based convertible, check that with a new kernel driver
(cros_ec_tbmc) that evtest collects tablet switch changes.
BUG=none
BRANCH=none
TEST=none
Change-Id: I40ce1a7d7c2fac768e5bbe7732572107207db36e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 87d5fb89fe
Original-Change-Id: I6821eaac1feb6c182bc973aaa2f747e687715afb
Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/430951
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://review.coreboot.org/18173
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/439306
Options with no prompt can go anywhere in the tree with the same
dependencies and they have the same effect. Moving them lower in
the tree allows the default values to be overridden by other Kconfig
files.
This patch just moves options with default values that aren't 'n'. The
'n' options are just removed in the next patch, since they aren't needed.
Verified that this makes no significant changes to any config file.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id189cd31a2b70a243905e84637b6f5811b435473
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e4aafb531
Original-Change-Id: I46175756b937a241edba87dbf70ce1be851fa89d
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17907
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/438350
For Kconfig options that we might want to override the default,
move the fallback default to the bottom of the file. This allows
the default to be set anywhere else, without requiring a select.
This is especially important for non-boolean symbols, which can't
have their defaults overridden in the Kconfig. Those can only be
updated in a saved config file.
Verified that this makes no significant changes to any config file.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1e206ae3857431c46b6ee9f1b3616231f5130075
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 75e5cb7a74
Original-Change-Id: I66034f356428f4ccd191d7420baf888edd5216dc
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17906
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/438060
When guado/rikku/tidus were rolled into jecht, an error was
made in set_power_led() as guado/rikku set the polarity
differently than tidus. Fix the power LED for guado/rikku
by setting the polarity correctly.
Test: boot guado/rikku and observe proper function of power LED
under S0, S3, and S5 power states.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibd9e844d796709ce93b275eb0c06c296ef7ed95f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aaa4ae766d
Original-Change-Id: I23072ac60bc9683776f748ca1326d98257c3c54f
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18249
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/438058
Bit 16 in BLC_PWM_CTL enables brightness controls, but the
current value is generic. Use the proper value, obtained
by reading BLC_PWM_CTL while running the VBIOS.
BUG=none
BRANCH=none
TEST=none
Change-Id: I338fa2a852165e882a613407739a438df58a6827
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3054ca164e
Original-Change-Id: Ib273359e1c285b405a9bb26fc217c2f7e255b99f
Original-Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Original-Reviewed-on: https://review.coreboot.org/10624
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/438057
The selection of the SSC reference frequency for LVDS was based on a
completely unrelated clock.
The `ssc_freq` flag should be set when the SSC reference runs at a
different frequency than the general display reference clock (DREF).
For most platforms, there is no choice, i.e. for i945 and gm45 the SSC
reference always differs from the display reference clock (i945: 66Mhz
SSC vs. 48MHz DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and
newer, it's the same frequency for SSC/non-SSC (120MHz). The only,
currently supported platform with a choice seems to be Pineview, where
the alternative is 100MHz vs. the default 96MHz.
BUG=none
BRANCH=none
TEST=none
Change-Id: I869be7519523453cd776fdc8c4cdc4dc0db03ad2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 561bebfbaa
Original-Change-Id: I7791754bd366c9fe6832c32eccef4657ba5f309b
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/18186
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/438055
The me_cleaner option is available on multiple platforms:
* Sandy and Ivy Bridge (well tested by multiple users).
* Skylake and Braswell (tested).
* Haswell, Broadwell and Bay Trail (untested).
The untested platforms have been included anyways because all the
firmwares are very similar and Intel ME/TXE probably behaves in the
same way.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8936047a8cd46d8982841cb16174362e8a8b45a4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 92e95cab96
Original-Change-Id: I46f461a1a7e058d57259f313142b00146f0196aa
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18206
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/438054
The WAK_STS bit is not set in a wake from G3, so the check for this
bit needs to only be done when checking for a wake from S3.
This change correctly enables the keyboard backlight in wake from G3
and only does not enable it during a wake from S3.
BUG=chrome-os-partner:58666
TEST=Use Refresh+Power to issue hard reset and ensure that the keyboard
backlight turns on like it does when waking from S5. Also force enter
hibernate with Alt+VolumeUp+H and then power back up and ensure that
the keyboard backlight is enabled when booting.
Change-Id: I9d74f798ee22aaf042c474212141676e4a3bf88d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 649100ad20
Original-Change-Id: I44045950e38aa5e5ae96a79385d604791852c7e6
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18280
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/438051
Reason for revert:
Pyro has two touchscreen sources: WACOM/ELAN.
It will not have both touchscreen IC in one system at the same time.
So the "probed" property of WACOM i2c device is mandatory to set for kernel
to know whether it exists before driver initializes it.
Otherwise in ELAN case, when driver fails to init WACOM i2c device, ACPI _OFF
will be invoked to set GPIO#152 low to cut off power.
BUG=chrome-os-partner:62371
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I2fc9f668bc20630d69026e4440142d05a01fd89b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b576e6f236
Original-Change-Id: I30f467bd8720d959686dc14f7877e6bc11ea6213
Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18291
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/438050
This change fixes the two sets of pins that were swapped in the
map of DQS signals from CPU to DRAM for channel 1.
Although this does not appear to have any impact to the system it
does result in different register values for DQS pin mapping that
are programmed inside FSP.
BUG=chrome-os-partner:58666
TEST=This fix was verified against the current schematic and using
FSP debug output.
Change-Id: I71df31ad94bc1fb8f16b6677c00f0ac997b4303a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9471d00a4f
Original-Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18279
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/438049
same change as I49935e659bf67225d3f5db1b06acc2cd046dcd74
this is required for poppy board as well.
GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals
when doing GPIO-driven I2S. This needs to be high by default so
the DSP can drive these signals, instead of low where it is enabled
for GPIO-driven I2S and the DSP cannot drive these signals.
BUG=None
BRANCH=None
TEST=play test sound in OS over internal speaker
Change-Id: I2d6d48a8cb67199ff76fc4056953a8c2194d74aa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 84394616df
Original-Change-Id: I1695e9198f8f78e9c5ad6df6c1ac073ac1762c6b
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18282
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/438048
GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals
when doing GPIO-driven I2S. This needs to be high by default so
the DSP can drive these signals, instead of low where it is enabled
for GPIO-driven I2S and the DSP cannot drive these signals.
BUG=chrome-os-partner:58666
TEST=play test sound in OS over internal speaker
Change-Id: Ife58cb27e3c1e0276a29ca5489fbc4c31402ba69
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5de37d5d7a
Original-Change-Id: I49935e659bf67225d3f5db1b06acc2cd046dcd74
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18281
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/438047
Add VFCT table to provide PCI Optiom Rom for
AMD graphic devices.
Useful for GNU Linux payloads and embedded dual GPU systems.
Tested on Lenovo T500 with AMD RV635 as secondary gpu.
Original Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic5f8c8122003d6f09b0ce2e663e31605daf7db7b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a5c2ac6256
Original-Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422
Original-Reviewed-on: https://review.coreboot.org/18192
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/438046
This allows for defaults to be applied to CMOS parameters
when cmos checksum is incorrect.
This probably results in changed cmos settings for current users of
these targets.
BUG=none
BRANCH=none
TEST=none
Change-Id: I28bec2270b9904c310408b15fa5a1fd2ff40a973
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 84e6881ba5
Original-Change-Id: Ifec0093f4b0dbaa51b96812a041f0eaf5c58ee86
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17041
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/437466
Adding spi_xfer_two_vectors as .xfer_vector for ipq40xx spi_ctrlr.
Commit 22e7b86790 ("UPSTREAM: spi: Get rid of SPI_ATOMIC_SEQUENCING")
has added new driver method xfer_vector to support combined write-read
operation within single CS cycle. The metohd is wrapped in
spi_xfer_vector() API. When spi_ctrlr structure does not have
xfer_vector method, API calls write and read operations sequentially.
However the QCA40xx SPI driver has "forced" CS activation-inactivation
in xfer method, so individual operation will break CS after write
operation, making combined write-read cycle broken.
Adding xfer_vector method to spi_ctrlr is quick fix to prevent this.
BUG=None
BRANCH=none
TEST=built and run on Gale
Change-Id: I031e85ce5b847353cb1084f6f68b2af8c6f702e1
Signed-off-by: Yuji Sasaki <sasakiy@google.com>
Reviewed-on: https://chromium-review.googlesource.com/433439
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kan Yan <kyan@google.com>
Activate the IOMMU for the ASUS F2A85-M LE board.
Enable the IOMMU in `devicetree.cb` and build AGESA IOMMU code by
enabling the option in `buildOpts.c`.
ACPI and MPTABLES interrupt routers are already present since they are
syminks to the F2A85-M version.
```
$ uname -a
Linux nukunuku 4.8.5 #35 SMP Sun Oct 30 19:34:55 CET 2016 x86_64 GNU/Linux
$ lspci -s 0.2
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit
$ dmesg | grep -i IOMMU
ACPI: IVRS 0x00000000BFFAFF70 000070 (v02 AMD AMDIOMMU 00000001 AMD 00000000)
AMD-Vi: Applying erratum 746 workaround for IOMMU at 0000:00:00.2
iommu: Adding device 0000:00:01.0 to group 0
[...]
iommu: Adding device 0000:00:18.5 to group 9
iommu: Adding device 0000:03:00.0 to group 8
AMD-Vi: Found IOMMU at 0000:00:00.2 cap 0x40
AMD IOMMUv2 driver by Joerg Roedel <jroedel@suse.de>
```
BUG=none
BRANCH=none
TEST=none
Change-Id: I3c758fb32becec6c5752a9e76af6345f37645078
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 31db6f5e17
Original-Change-Id: I6049fcfad53d16a99495d7a8fbc584c71e371d73
Original-Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Reviewed-on: https://review.coreboot.org/18259
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/437465
Add new ChromeOS devices banjo, candy, clapper, glimmer, gnawty,
heli, kip, orco, quawks, squawks, sumo, swanky, and winky using
their common reference board (rambi) as a base.
Chromium sources used:
firmware-banjo-5216.334.B 32ec493 [chromeos: vboot_loader: Set...]
firmware-candy-5216.310.B 519ff11 [baytrail: Preserve VbNv around...]
firmware-clapper-5216.199.B 80d55e3 [baytrail: add code for...]
firmware-glimmer-5216.198.B fae0770 [baytrail: add code for...]
firmware-gnawty-5216.239.B 952adb7 [Gnawty/Olay: Add 2nd source...]
firmware-heli-5216.392.B f1f3604 [helis: Lock ME / TXE section...]
firmware-kip-5216.227.B db3c5d9 [kip: update spd for for MT41K256M16*]
firmware-orco-5216.362.B 76f1651 [Orco: Adjust rx delay for norm.]
firmware-quawks-5216.204.B edb60c9 [Quawks: Update SPD data]
firmware-squawks-5216.152.B c6573dc [Squawks: Update SPD data]
firmware-sumo-5216.382.B c62b6f23 [Ninja, Sumo: Add SPD source...]
firmware-swanky-5216.238.B 233b2a7 [Swanky: update SPD table]
firmware-winky-5216.265.B ce91ffc [Add to support HT Micron...]
The same basic cleanup/changes are made here as with the initial BYT
variant commit:
- remove unused ACPI trackpad/touchscreen devices
- correct I2C addresses in SMBIOS entries
- clean up comment formatting
- remove ACPI device for unused light sensor
- switch I2C ACPI devices from edge to level triggered interrupts,
for better compatibility/functionality (and to be consistent
with other recently-upstreamed ChromeOS devices)
- Micron 2GB SPD file for kip with updated values renamed to distinguish
from same file used by other boards
BUG=none
BRANCH=none
TEST=none
Change-Id: I26f12b3bb2f4b99d751ac5e8f26e268f31d4e562
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9be3f5dab4
Original-Change-Id: Ic66f9b539afb5aff32c4c1a8563f6612f5a2927c
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18164
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/435813
This patch sets PL2 override value to 15W in RAPL registers.
BUG=chrome-os-partner:62110
BRANCH=reef
TEST=Apply new firmware to evaluate Octane benchmark score.
Change-Id: Ica8efcff11cf5683d9bec9b249d05ef8db81f44d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4a282b8419
Original-Change-Id: I51734051586753677129314b5273fb275c74f5d2
Original-Signed-off-by: Harry Pan <harry.pan@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18283
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/437464
This mainboard is based on Intel's Leafhill CRB with Apollo Lake
silicon. In a first step, it concerns only a copy of intel/leafhill
directory with minimum changes. Special adaptations for MC APL1
mainboard will follow in separate commits.
BUG=none
BRANCH=none
TEST=none
Change-Id: I060d63edb5a4fcdc857aa419ac66a95ec983910b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 092db95742
Original-Change-Id: If0b8a2bc21c99c3be4e6043e8febfb1b91ff0a63
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/18272
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/435811
That status isn't needed and making it non-static helps gcc 4.9.2 (or
any compiler that insists on "standard C" behaviour with global const
initializers)
BUG=none
BRANCH=none
TEST=none
Change-Id: I90c0d1ce22365b2276cf173f1e95d22ea50963a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c09e148b38
Original-Change-Id: Ib1fbd5213d262e653f31564b106095b4a28292f6
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://review.coreboot.org/18266
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/435259
We rely on gnu make, so we can expect the jobserver to be around in
parallel builds, too. Avoids some make warnings and slightly speeds up
the build if those sub-makes are executed (eg for arm-trusted-firmware
and vboot).
BUG=none
BRANCH=none
TEST=none
Change-Id: I858f72696b7a3f3491ca950b4374735cbb363bb7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 78a5f22994
Original-Change-Id: I0e6a77f2813f7453d53e88e0214ad8c1b8689042
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://review.coreboot.org/18263
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/435403
Reorder the items to minimize the differences.
BUG=none
BRANCH=none
TEST=none
Change-Id: I56a151e717f7ca3f8a3f9ca4106dfc73ea2be963
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7328cf948e
Original-Change-Id: I745ec70a990f997d87c2a0b6164ae127eb694ddf
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/17438
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/435401
The rule to make spd.bin that's in src/lib is for the 'generic_spd_bin'
implementation. It wasn't guarded though, so it was generating a build
warning for any other platform that generated an spd.bin file.
Sample warning that this fixes:
src/mainboard/gizmosphere/gizmo/Makefile.inc:42:
warning: overriding recipe for target 'build/spd.bin'
src/lib/Makefile.inc:298: warning: ignoring old recipe for target
'build/spd.bin'
BUG=none
BRANCH=none
TEST=none
Change-Id: I830ec92595c25005930599c02b5e1c71dc8e87bd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e4bb3164a
Original-Change-Id: Iadd6743f8ae476969bf36f99b918f04c04172d1d
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18261
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/435400
Apollolake boards should use DMIC-4ch configuration in Kernel side and
use CaptureChannelMap in userspace to distinguish boards with different
number of DMIC's. So, NHLT DMIC 1-ch & 2-ch endpoint configuration will
not be required and hence removed.
BUG=chrome-os-partner:60827
TEST=Verify internal mic capture
TEST='arecord -Dhw:0,3 dmic_4ch.wav -f S16_LE -r 48000 -c 4 -d 10' works
Change-Id: I7c66d5d7b22826c4141a3551624ef6c9b5163d73
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 545edca577
Original-Change-Id: Ibe81290906c9e379ae49e437648ee9cd6f123ff8
Original-Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18252
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/435399
EC sets the logic level based on outstanding wake events. When GPIO_22
is configured as a level triggered interrupt, the events are not
cleared from the interrupt handler. Hence, we'd just be re-signalling
over and over causing an interrupt storm upon lid open. So, GPIO_22
needs to be configured as EDGE_SINGLE instead of LEVEL.
BUG=chrome-os-partner:62458
TEST=Lid close/open. check CPU usage using top. It should
not show 70% CPU usage.
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Change-Id: I5c6a65c35d217d4c62dcde004f78f024332cb3b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6e5609124e
Original-Change-Id: I710a690578c6e5b63be34b7fbcb21c703ef56e3a
Original-Reviewed-on: https://review.coreboot.org/18267
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/435398
For the boards that intend to use mock tpm and have recovery mrc cache
support enabled, provide mock functions to read and write mrc hash
space.
Reading MRC hash space returns TPM_SUCCESS as later checks take care of
comparing the hash value and retraining if hash comparison fails. Thus,
in case of mock tpm, device would always end up doing the memory
retraining in recovery mode.
BUG=chrome-os-partner:62413
BRANCH=None
TEST=Verified that eve builds with mock tpm selected.
Change-Id: Ib946ea2044a64286495a20a285ae5200702c24c9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 775765eaf3
Original-Change-Id: I7817cda7821fadeea0e887cb9860804256dabfd9
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18248
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/435338
In some cases, we don't want the Chrome EC firmwares (both EC and PD)
built directly by the coreboot build system or included in images at
all. This is already supported with EC_EXTERNAL_FIRMWARE but it does
implement a binary (build and include) or (neither build nor include)
policy.
Some cases require the ability to separately control whether the EC
and PD firmwares should be built and included by the coreboot build
system, only included from externally-built images or not included
at all.
This introduces config changes implementing that behaviour, renaming
options to make it clear that they are specific to the Chrome EC.
BUG=none
BRANCH=none
TEST=none
CQ-DEPEND=CL:434278
Change-Id: Ie0b9e2063280a2b596a2d43afae855401319a959
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ff24803a3
Original-Change-Id: I44ccee715419360eb7d83863f4f134fcda14a8e4
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/16033
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430678
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
1. For ELAN, export reset GPIO as well as PowerResource
2. For WCOM, export PowerResource
BUG=chrome-os-partner:62311, chrome-os-partner:60194,
chrome-os-partner:62371
BRANCH=reef
TEST=Verified that touchscreen works on pyro with WCOM device on
power-on as well as after suspend/resume.
Change-Id: I5bc6c4d79d9606319c54ed3521b6ac2176ac51ca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a7a517ddc5
Original-Change-Id: I0306e24e19bf821cd3e08fdacc0d78b494c9a92f
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18239
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/434480
Linux kernel expects that power management with ACPI should always be
handled using PowerResource. However, some kernel drivers (e.g. ELAN
touchscreen) check to see if reset gpio is passed in by the BIOS to
decide whether the device loses power in suspend. Thus, until the kernel
has a better way for drivers to query if device lost power in suspend,
we need to allow passing in of GPIOs via _CRS as well as exporting
PowerResource to control power to the device.
Update mainboards to export reset GPIO as well as PowerResource for
ELAN touchscreen device.
BUG=chrome-os-partner:62311,chrome-os-partner:60194
BRANCH=reef
TEST=Verified that touchscreen works on power-on as well as after
suspend-resume.
Change-Id: Ice3b1040d4cda0e5ac6d2a1f211dc8c8d78668cc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 71d830fddc
Original-Change-Id: I3409689cf56bfddd321402ad5dda3fc8762e6bc6
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18238
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/434479
I2C data (GPIO_132) and Clk (GPIO_133) lines are pulled low during
standby states S3/S0ix. This causes leakage of power. To reduce the
leakage, we have to pull these lines high during S3/S0ix. This is
done by programming the IOSSTATE to HIz. Also note that we are using
the internal pull ups to keep at SOC at 1.8V and the I2C lines are
not floating.
BUG=chrome-os-partner:62428,chrome-os-partner:61651
TEST=Enter S3/S0ix. Measure trackpad power. It should be less
than 4mW. Also I2c lines should be pulled high in S3/S0ix.
Change-Id: Icd735ff83676dd179eaa6c38bb2c25562ac3905a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f224e836c0
Original-Change-Id: I5570ac37ec3cc41f6463dd6b858fdb56a20a1733
Original-Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18251
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/434478
There will be more follow-up changes.
BUG=chrome-os-partner:62377
BRANCH=None
TEST=emerge-scarlet coreboot libpayload
Change-Id: I4804239483f8b35bc3703aa62c2a8fd642e0234a
Signed-off-by: philipchen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/433039
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
If cmos is invalid, it doesn't make sense to read the value before
finding that out.
BUG=none
BRANCH=none
TEST=none
Change-Id: I99768c9fee002d965c8e98e36f5d385f9e9cd861
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0e7a93fa65
Original-Change-Id: Ieb4661aad7e4d640772325c3c6b184de1947edc3
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18236
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/433882
The default macaddress in rt8168.c can be changed with a cbfsfile
called macaddress. This patch makes it possible to add such a file
using Kconfig at build time.
This also changes the name of the cbfsfile from "macaddress" to
"rt8168-macaddress" to avoid confusion.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib9c2286a9a382131cb1d1302202846b62c508f49
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ec74f45e72
Original-Change-Id: I24674d8df11845167b837b79344427ce0c67f4fb
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18088
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/433881
Ubuntus default compiler flags for GCC [1][2] include `-Wformat
-Wformat-security`, causing errors similar like the one below.
```
CC romstage/northbridge/amd/amdht/ht_wrapper.o
src/northbridge/amd/amdht/ht_wrapper.c: In function 'AMD_CB_EventNotify':
src/northbridge/amd/amdht/ht_wrapper.c:124:4: error: format not a string literal and no format arguments [-Werror=format-security]
printk(log_level, event_class_string_decodes[evtClass]);
^
[]
```
Fix that, by explicitly using a format string.
TEST=Built and booted on ASUS KGPE-D16.
[1] https://stackoverflow.com/questions/17260409/fprintf-error-format-not-a-string-literal-and-no-format-arguments-werror-for
"fprintf, error: format not a string literal and no format arguments [-Werror=format-security"
[2] I tested with gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609.
Change-Id: Iff829bf83e1ead8537fbe5d7c5c6376bdd77f323
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f6776fa62c
Original-Change-Id: Iabe60deeffa441146eab31dac4416846ce95c32a
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18208
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/433880
Wacom touchscreen is i2c hid device and it's the device that always
exists.
So no need to set "probed" property for it.
BUG=chrome-os-partner:61513
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I6715126e4aaa9e133fefc2eaa9c7457654e99af3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fe8a01b01a
Original-Change-Id: I27fe18ceadd03029b826e0237f80132eda1089b0
Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18227
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/433878
Add support for Lenovo Thinkpad L520.
The files are generated by autoport,
and are successfully tested on the board.
L520 has got 4MiB flash chip, that contains a "slim" ME
with 1.2MiB only. The flash IC has to be desoldered, as
it won't be accessible in circuit. It is located on top
of the mainboard right under the touchpad.
Test-setup:
Extract the following blobs from vendor BIOS:
* Intel Flash Descriptor
* Intel Management Engine
* Intel VBios
The laptop has been externaly flashed. It was able to
turn on the display and load SeaBIOS.
Latest debian has been booted from harddisk.
Latest fedora has been booted from USB flash drive.
The following hardware has been tested and is working:
* Display using Option Rom
* PCIe wifi
* Ethernet
* Keyboard, trackpoint and touchpad
* Some Fn functions keys
* Volume Keys (except mic mute)
* Status LEDs
* Audio (headphone jack only)
* USB ports
* Native raminit dual channel (2 DDR3-1333 DIMMs tested)
* SATA cdrom
* SATA harddrive
Broken:
* Some Fn functions keys
* Microphone mute button
* Speakers (but headphone jack gives sound)
Untested:
* Expansion slot
* SD card slot
* Docking station
* Native gfx init
The EHCI debug port is the first one on the right side.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie7b248243339b52e6120c18ed217a740bc8992cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aae6e9cfe9
Original-Change-Id: Ic8943799b953bde09ff1daf8427ce5125a0778ca
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18003
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/431982
This fixes building coreboot with -std=gnu11 on gcc 4.9.x
Also needs fix ups for asus/kcma-d8 and asus/kgpe-d16 due to the missing
type.
BUG=none
BRANCH=none
TEST=none
Change-Id: I815127db725dd4bc3930e361d79d27a2a63eca80
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 06a629e4b1
Original-Change-Id: I920d492a1422433d7d4b4659b27f5a22914bc438
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18220
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/431985
This commit makes the initial changes to support the Intel Leaf Hill
CRB with Apollo Lake silicon. Memory parameters and some GPIOs are set.
The google/reef directory is used as a template, and the same IFWI
stitching process as reef is used to generate a bootable image.
Apollo Lake silicon requires a boot media region called IFWI which includes
assets such as CSE firmware, PMC microcode, CPU microcode, and boot
firmware.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1fb1184c5177437cc19824c14ec629440aaede80
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dcc0aa84fa
Original-Change-Id: Id92f0458548e3054d86f5faa8152d58d902f4418
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18039
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/431980
o Fix indentation and other whitespace issues,
o Use `const` where applicable,
o Avoid retyping the same constant literals,
o Actually read PCI revision from the device (instead of using the
lowest class byte).
BUG=none
BRANCH=none
TEST=none
Change-Id: I74c9feb687e8e8b42aeeb4ed7265547f289fd427
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d37fa8d84d
Original-Change-Id: I2c64153c61a51a6a87848360d22f981225812a3b
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/18185
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/431979
