various cleanups from upstream

These were done during upstreaming (ie. to the commits directly), so
there's no correspondence as individual CLs for these.
The "Reviewed-on" list below is a catch-all to help gerrit-rebase ignore
changes that were handled one way or another but aren't tracked.

BUG=none
BRANCH=none
TEST=with various up/downstreaming CLs merged,
$ git diff --stat cros/chromeos-2016.05 origin/master # has only a very
small set of remaining changes (COMMIT-QUEUE.ini etc, git submodules)

Change-Id: I9c2cee7fbadbc1393ca0fb1c3b4f7a1ddb48341b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Ignore-CL-Reviewed-on: https://review.coreboot.org/15122
Ignore-CL-Reviewed-on: https://review.coreboot.org/15604
Ignore-CL-Reviewed-on: https://review.coreboot.org/15919
Ignore-CL-Reviewed-on: https://review.coreboot.org/16021
Ignore-CL-Reviewed-on: https://review.coreboot.org/16055
Ignore-CL-Reviewed-on: https://review.coreboot.org/16253
Ignore-CL-Reviewed-on: https://review.coreboot.org/17061
Ignore-CL-Reviewed-on: https://review.coreboot.org/17179
Ignore-CL-Reviewed-on: https://review.coreboot.org/17185
Ignore-CL-Reviewed-on: https://review.coreboot.org/17340
Ignore-CL-Reviewed-on: https://review.coreboot.org/17366
Ignore-CL-Reviewed-on: https://review.coreboot.org/17775
Ignore-CL-Reviewed-on: https://review.coreboot.org/17872
Ignore-CL-Reviewed-on: https://review.coreboot.org/17875
Ignore-CL-Reviewed-on: https://review.coreboot.org/17962
Ignore-CL-Reviewed-on: https://review.coreboot.org/18023
Ignore-CL-Reviewed-on: https://review.coreboot.org/18158
Ignore-CL-Reviewed-on: https://review.coreboot.org/18170
Ignore-CL-Reviewed-on: https://review.coreboot.org/18171
Ignore-CL-Reviewed-on: https://review.coreboot.org/18172
Ignore-CL-Reviewed-on: https://review.coreboot.org/18205
Reviewed-on: https://chromium-review.googlesource.com/427824
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>

payloads/libpayload/drivers/timer/Kconfig

@@ -10,7 +10,6 @@
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
 
-
 config TIMER_RDTSC
 	bool
 	default y

src/drivers/parade/ps8640/ps8640.c

@@ -77,7 +77,7 @@ int ps8640_init(uint8_t bus, uint8_t chip)
 
 	mdelay(50);
 
-	/**
+	/*
 	 * The Manufacturer Command Set (MCS) is a device dependent interface
 	 * intended for factory programming of the display module default
 	 * parameters. Once the display module is configured, the MCS shall be

src/drivers/spi/cbfs_spi.c

@@ -34,7 +34,7 @@ static struct spi_flash *spi_flash_info;
  *
  * read SPI 62854 7db7: 10416 us, 3089 KB/s, 24.712 Mbps
  *
- * The important number is the last one. It should roughyly match your SPI
+ * The important number is the last one. It should roughly match your SPI
  * clock. If it doesn't, your driver might need a little tuning.
  */
 #define SPI_SPEED_DEBUG		0
@@ -43,7 +43,7 @@ static ssize_t spi_readat(const struct region_device *rd, void *b,
 				size_t offset, size_t size)
 {
 	struct stopwatch sw;
-	bool show = SPI_SPEED_DEBUG && size >= 4*KiB;
+	bool show = SPI_SPEED_DEBUG && size >= 4 * KiB;
 
 	if (show)
 		stopwatch_init(&sw);

src/drivers/spi/tpm/Kconfig

@@ -8,6 +8,6 @@ config DRIVER_TPM_SPI_BUS
 	depends on SPI_TPM
 
 config DRIVER_TPM_SPI_CHIP
-       int "Chip Select of the TPM chip on its SPI bus"
-       default 0
-       depends on SPI_TPM
+	int "Chip Select of the TPM chip on its SPI bus"
+	default 0
+	depends on SPI_TPM

src/mainboard/google/gru/mainboard.c

@@ -75,10 +75,11 @@ static void register_apio_suspend(void)
 static void register_gpio_suspend(void)
 {
 	/*
-	 * these 3 pin to disable gpio2 ~ gpio4 1.5v, 1.8v, 3.3v power supply
-	 * so need to shut down the power supply from high voltage to
-	 * low voltage, and consider register_bl31() appends to the front off
-	 * the list, we should register 1.5v enable pin to 3.3v enable pin
+	 * These three GPIO params are used to shut down the 1.5V, 1.8V and
+	 * 3.3V power rails, which need to be shut down ordered by voltage,
+	 * with highest voltage first.
+	 * Since register_bl31() appends to the front of the list, we need to
+	 * register them backwards, with 1.5V coming first.
 	 */
 	static struct bl31_gpio_param param_p15_en = {
 		.h = {

src/mainboard/google/gru/romstage.c

@@ -42,8 +42,10 @@ static void init_dvs_outputs(void)
 
 static void prepare_usb(void)
 {
-	/* Do dwc3 core soft reset and phy reset. Kick these resets
-	 * off early so they get at least 100ms to settle. */
+	/*
+	 * Do dwc3 core soft reset and phy reset. Kick these resets
+	 * off early so they get at least 100ms to settle.
+	 */
 	reset_usb_otg0();
 	reset_usb_otg1();
 }

src/soc/mediatek/mt8173/dsi.c

@@ -310,7 +310,7 @@ void mtk_dsi_pin_drv_ctrl(void)
 
 	do {
 		if (stopwatch_expired(&sw)) {
-			printk(BIOS_ERR, "enable lvdstx_power fail!!!\n");
+			printk(BIOS_ERR, "enable lvdstx_power failed!!!\n");
 			return;
 		}
 	} while ((read32(&lvds_tx1->vopll_ctl3) & RG_AD_LVDSTX_PWR_ACK) == 0);

src/soc/rockchip/rk3399/Makefile.inc

@@ -64,15 +64,15 @@ ramstage-y += sdram.c
 ramstage-y += ../common/spi.c
 ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
 ramstage-y += clock.c
-ramstage-y += display.c
-ramstage-y += ../common/edp.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/edp.c
 ramstage-y += ../common/gpio.c
 ramstage-y += gpio.c
 ramstage-y += ../common/i2c.c
 ramstage-y += saradc.c
 ramstage-y += soc.c
 ramstage-y += timer.c
-ramstage-y += ../common/vop.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/vop.c
 ramstage-y += usb.c
 
 ramstage-y += bl31_plat_params.c

src/soc/rockchip/rk3399/clock.c

@@ -409,7 +409,7 @@ void rkclk_init(void)
 
 	/* configure pmu pclk */
 	pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
-	assert((unsigned)(PPLL_HZ - (pclk_div + 1) * PMU_PCLK_HZ) <= pclk_div
+	assert((unsigned int)(PPLL_HZ - (pclk_div + 1) * PMU_PCLK_HZ) <= pclk_div
 	       && pclk_div <= 0x1f);
 	write32(&pmucru_ptr->pmucru_clksel[0],
 		RK_CLRSETBITS(PMU_PCLK_DIV_CON_MASK << PMU_PCLK_DIV_CON_SHIFT,
@@ -508,6 +508,7 @@ void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster)
 		pll_con = &cru_ptr->apll_l_con[0];
 		break;
 	case CPU_CLUSTER_BIG:
+	default:
 		con_base = 2;
 		parent = CLK_CORE_PLL_SEL_ABPLL;
 		pll_con = &cru_ptr->apll_b_con[0];

src/soc/rockchip/rk3399/sdram.c

@@ -450,11 +450,11 @@ static void phy_io_config(u32 channel,
 
 
 	/* speed setting */
-	if (sdram_params->ddr_freq < 400*MHz)
+	if (sdram_params->ddr_freq < 400 * MHz)
 		speed = 0x0;
-	else if (sdram_params->ddr_freq < 800*MHz)
+	else if (sdram_params->ddr_freq < 800 * MHz)
 		speed = 0x1;
-	else if (sdram_params->ddr_freq < 1200*MHz)
+	else if (sdram_params->ddr_freq < 1200 * MHz)
 		speed = 0x2;
 	else
 		speed = 0x3;
@@ -566,11 +566,7 @@ static int pctl_cfg(u32 channel,
 	/* PHY_DLL_RST_EN */
 	clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
 
-	/*
-	 * FIXME:
-	 * need to care ERROR bit,
-	 * if 100ms do not get right status, return err
-	 */
+	/* FIXME: need to care ERROR bit */
 	stopwatch_init_msecs_expire(&sw, 100);
 	while (!(read32(&denali_ctl[203]) & (1 << 3))) {
 		if (stopwatch_expired(&sw))
@@ -1019,7 +1015,7 @@ void sdram_init(const struct rk3399_sdram_params *sdram_params)
 			udelay(10);
 
 		if (data_training(channel, sdram_params, PI_FULL_TRAINING)) {
-			printk(BIOS_DEBUG,
+			printk(BIOS_ERR,
 			       "SDRAM initialization failed, reset\n");
 			hard_reset();
 		}

src/soc/rockchip/rk3399/soc.c

@@ -38,10 +38,10 @@ static void soc_init(device_t dev)
 	 */
 	mmio_resource(dev, 1, (0x10000 / KiB), (0x80000 / KiB));
 
-	if (display_init_required())
+	if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) && display_init_required())
 		rk_display_init(dev);
 	else
-		printk(BIOS_INFO, "Skipping display init.\n");
+		printk(BIOS_INFO, "Display initialization disabled.\n");
 
 	/* We don't need big CPUs, but bring them up as a courtesy to Linux. */
 	rkclk_configure_cpu(APLL_600_MHZ, CPU_CLUSTER_BIG);

util/cbfstool/cbfs-payload-linux.c

@@ -252,7 +252,7 @@ int parse_bzImage_to_payload(const struct buffer *input,
 	}
 
 	unsigned long kernel_base = 0x100000;
-	if ((hdr->protocol_version >= 0x200) && (!hdr->loadflags)) {
+	if ((hdr->protocol_version < 0x200) || !(hdr->loadflags & 1)) {
 		kernel_base = 0x1000; /* zImage kernel */
 	}
 	/* kernel prefers an address, so listen */