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UPSTREAM: nb/intel/pineview: Make preallocated igd memory a cmos parameter

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BUG=none
BRANCH=none
TEST=none

Change-Id: I2d057e7764b7eeb21208d9b6709e63c5198ba9f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2a0e998ec2
Original-Change-Id: Ia7fa2c290e540ff779cf8dc16147db5a248021e2
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18142
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/432760
This commit is contained in:
Arthur Heymans 2017-01-14 17:32:20 +01:00 • committed by chrome-bot
commit 61c1644317
1 changed files with 11 additions and 1 deletions
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12
src/northbridge/intel/pineview/early_init.c
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@ -25,6 +25,7 @@
#include <string.h>
#include <northbridge/intel/pineview/pineview.h>
#include <northbridge/intel/pineview/chip.h>
#include <pc80/mc146818rtc.h>
#define LPC PCI_DEV(0, 0x1f, 0)
#define D0F0 PCI_DEV(0, 0, 0)
@ -45,7 +46,16 @@ static void early_graphics_setup(void)
const struct northbridge_intel_pineview_config *config = d0f0->chip_info;
pci_write_config8(D0F0, DEVEN, BOARD_DEVEN);
pci_write_config16(D0F0, GGC, 0x130); /* 1MB GTT 8MB UMA */
/* vram size from cmos option */
if (get_option(&reg8, "gfx_uma_size") != CB_SUCCESS)
reg8 = 0; /* 0 for 8MB */
/* make sure no invalid setting is used */
if (reg8 > 6)
reg8 = 0;
/* Select 1M GTT */
pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, (1 << 8)
| ((reg8 + 3) << 4));
printk(BIOS_SPEW, "Set GFX clocks...");
reg16 = MCHBAR16(MCH_GCFGC);