This needs some extra headers in amdk8/raminit.c that were otherwise
provided by that file.
BUG=none
BRANCH=none
TEST=none
Change-Id: I93fc04d84b412f5db1c80766f28d1f31d8d8fe6a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 3eff00ec76
Original-Change-Id: I80450e5eb32eb502b3d777c56790db90491fc995
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19360
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490681
Add a check for vboot when locating the binaryPI image.
There is currently an ordering problem using cbmem to locate the
image when vboot is present. Vboot inserts its locator into the
search process so that memory can be checked before flash is queried.
For the earliest calls using the wrapper, DRAM has not been set up
and cbmem not initialized in romstage. This change prevents an
endless loop when vboot searches cbmem.
This change has another side effect. When vboot is in effect, the
change forces the RO binaryPI to be used even when on either of the
RW paths. There is currently no ability to relocate the XIP image
for use in a RW region.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 6efe9217c38cf93fd9b38e52cf3ec90fee3d0474)
BUG=none
BRANCH=none
TEST=none
Change-Id: If30b23954f97cc4565ff81b55ee3a9e4145be379
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ca3815b4c5
Original-Change-Id: I0c14bd729f8a67bca37cbdbd3a5e266c99c86d54
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18438
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490076
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
The devicetree data structures have been available in more than just
ramstage and romstage. In order to provide clearer and consistent
semantics two new macros are provided:
1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE
2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST
The ROMSTAGE_CONST attribute is used in the source code to mark
the devicetree data structures as const in early stages even though
it's not just romstage. Therefore, rename the attribute to
DEVTREE_CONST as that's the actual usage. The only place where the
usage was not devicetree related is console_loglevel, but the same
name was used for consistency. Any stage that is not ramstage has
the const C attribute applied when DEVTREE_CONST is used.
BUG=none
BRANCH=none
TEST=none
Change-Id: If0409e8e9d6a203254a9f9b749de5cab70dfc842
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e4d7abc0d4
Original-Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19333
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/488047
For raminit to succeed on a hot reset the following things are
prevented from running:
* Clearing self refresh
* Setting memory frequency
* programming sdram dll timings
* programming rcomp
TESTED on Intel d510mo.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3c561f2bcffeb7e76159c529049c7aaeb7143a13
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00fd3ff507
Original-Change-Id: I8f7e5c2958df29a96cdf856ade2f4f33707ad362
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19337
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/486761
The function decode_spd uses undeclared variables and an incorrectly
initialized array.
BUG=none
BRANCH=none
TEST=none
Change-Id: I896b374368ecc4e217297402ac98d93a059bf4c3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 097d753980
Original-Change-Id: Ib45a8b2946c04c270e29524675b1f09d491d282b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19336
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/486741
Hide some (partial) lines behind DEBUG_RAM_SETUP and shorten
some messages. This saves some KiB to make CBMEM console more
usable in romstage.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia059932c6328ea4dab09714dd2a9eca2b00808b9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0624f92118
Original-Change-Id: I62a84ca662ee778b7c1deb71247f3b01a37858fa
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19318
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/482963
Adds the necessary plumbing for acpi_device_path() to find the LPC
bridge on the AMD Family10h/15h northbridges and SB700 southbridge.
This is necessary for TPM support since the acpi path to the LPC bridge
doesn't match the built-in default in tpm.c
This is a port of GIT hash d8a2c1fb by Tobias Diedrich.
BUG=https://ticket.coreboot.org/issues/102
Change-Id: I119547820e94fd1cd2baf814ef2595b43362efe0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0f3a18ad28
Original-Change-Id: I1c514e335e194b2864599e5419cfaee830b94e38
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/19282
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/480297
The x4x northbridge can be paired with either an ICH7 (in the case of
g41) or an ICH10 (all other cases: g45, q45, p45, ...). Only ICH10
sometimes occurs with a descriptor, gbe and an ME region.
ICH7 is always descriptorless so it makes no sense to fix CBFS to
accommodate for those other objects.
BUG=none
BRANCH=none
TEST=none
Change-Id: I150ac6c49ed853522802c5c948c61699fe123925
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4bc9c28811
Original-Change-Id: I4a01dfdbce1807e44932a3ac812110382332abd8
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19181
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/480289
Includes the DRAM controller device that knows which where the division
between addresses routed to the main memory and to the PCI bus is.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9246a4b6ddeec914efe99c2df7b13eeb5166577d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 38d1eb4403
Original-Change-Id: Id4cfeb8ff32de37723eee68a61c576e657dad30b
Original-Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Original-Reviewed-on: https://review.coreboot.org/18896
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480280
This is the actual PCI Id of the internal graphics.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4b703e94434fc2a6fb13a17dff29f030dc4933c4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 43156f6625
Original-Change-Id: I2a25ed35a5b01de6da905619fa9fce96738d1c0e
Original-Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Original-Reviewed-on: https://review.coreboot.org/18895
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/480279
Without them the BS_DEV_RESOURCES stage won't traverse the bridge and
the graphics controller would be left without resources assigned.
Even worse, the resources would stay based in offset 0 which confuses
the MTRR setting code and causes a good chunk of the DRAM to be set
to type write combining.
With the patch applied, the resources are set:
Show resources in subtree (Root Device)...After assigning values.
...
PCI: 00:01.0 child on link 0 PCI: 01:00.0
+ PCI: 00:01.0 resource base ffff size 0 align 0 gran 0 limit ffff flags 60080100 index 0
+ PCI: 00:01.0 resource base f8000000 size 4000000 align 26 gran 0 limit fbffffff flags 60081200 index 1
+ PCI: 00:01.0 resource base fc000000 size 1010000 align 24 gran 0 limit fd00ffff flags 60080200 index 2
PCI: 01:00.0
- PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10
- PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14
- PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
+ PCI: 01:00.0 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60001200 index 10
+ PCI: 01:00.0 resource base fc000000 size 1000000 align 24 gran 24 limit fcffffff flags 60000200 index 14
+ PCI: 01:00.0 resource base fd000000 size 10000 align 16 gran 16 limit fd00ffff flags 60002200 index 30
And the caching mode is set properly:
MTRR: Physical address space:
-0x0000000000000000 - 0x0000000004000000 size 0x04000000 type 1
-0x0000000004000000 - 0x000000000e000000 size 0x0a000000 type 6
-0x000000000e000000 - 0x0000000100000000 size 0xf2000000 type 0
+0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
+0x00000000000c0000 - 0x000000000e000000 size 0x0df40000 type 6
+0x000000000e000000 - 0x00000000f8000000 size 0xea000000 type 0
+0x00000000f8000000 - 0x00000000fc000000 size 0x04000000 type 1
+0x00000000fc000000 - 0x0000000100000000 size 0x04000000 type 0
The problem was also spot and discussed here:
http://coreboot.coreboot.narkive.com/E9eGauzH/via-c7-on-bcom-winnet-p680-l1-l2-cache-very-slow
BUG=none
BRANCH=none
TEST=none
Change-Id: I5368a607d44f0f0afae0a3d1ecc424f0fa8cb9bd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2523dd031c
Original-Change-Id: Idb4979b206838dd6455b2a16de14dc74f83af921
Original-Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Original-Reviewed-on: https://review.coreboot.org/18894
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480278
Otherwise, it locks up quickly. Not sure which ones are actually needed
and why, couldn't bisect it into removing even a single one.
The factory BIOS on a Neoware G170 does 200 0xed reads between setting
the registers too.
BUG=none
BRANCH=none
TEST=none
Change-Id: I11e149bad93bc05eb6e7ef8373ad4ae834d02633
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b31a066e0d
Original-Change-Id: I6aa38768d84dd42c9c720c917a99e6b4b1e03427
Original-Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Original-Reviewed-on: https://review.coreboot.org/18893
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480110
Vendor BIOS leaves UPMC1 untouched (on 945gc the default is 0x0203).
Not running PCIEx16 init which is valid for 945gm seems to fix all
issues and instabilities related to the PEG port.
According to lspci the link width is at the desired x16.
It is unknown if devices requesting a lower width work automatically
or need more configuration.
What happens is that IGD gets disabled by the disable function in
gma.c when an external GPU is found unless
CONFIG_ONBOARD_VGA_IS_PRIMARY is set.
Setting IGD as secondary makes Linux (4.10) hang, so this behavior is
a requirement for now.
TESTED on P5GC-MX with a discrete GPU and both
CONFIG_ONBOARD_VGA_IS_PRIMARY set and unset.
BUG=none
BRANCH=none
TEST=none
Change-Id: I305d73ec4472f7df1618d5da29853ffcfb048e30
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2f6b52e3a0
Original-Change-Id: I6da8aa7714073f4b34df5ae3c1eb4c19e27ddc97
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18549
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/480104
This is needed if one wants to use the header more than once.
BUG=none
BRANCH=none
TEST=none
Change-Id: If43ac3dafbb8e6b9052d6af9206d586d5a466ce1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f170e71630
Original-Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19029
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/474135
All boards select INTEL_EDID, move it to nb folder.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie41e0d5dc6a50e9b2ba170cf1ad6c25b74a47f2e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 46cf5c29b3
Original-Change-Id: I35f075a87f2d841856b208f9440cf41af6a3c8e6
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19086
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/472711
Move odt stretch into own function.
Apply workaround on SandyBridge C-stepping CPU only.
Apply odt stretch on all other CPU types.
Don't depend on empty DIMM detection, as in case one slot
is empty ref_card_offset is zero.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie348a49ed33b841503f0e54b24969f7faf02b546
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 19c3dad0ad
Original-Change-Id: I4320f14e0522ec997b1f9f3b12ba2c2070ee8e9e
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17616
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/472709
quick_ram_check doesn't change contents of memory.
Run it in S3 resume, too.
BUG=none
BRANCH=none
TEST=none
Change-Id: I903fd25adfa117b0b466a7c191ae2bf54d7af867
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 77db3e153b
Original-Change-Id: Icaf3650fadbb3bb87d8c780a9e79737c3cf7eb06
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17615
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/472708
Silency noisy raminit logging by:
* Removing verbose logging from loops.
* Printing detailed summary at end of loop instead.
* Using the same scheme already present in some functions.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1f947fcece53776fa71c55a5557c57ef526c91a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 368b615243
Original-Change-Id: I412d81592436ac0d2422caf396c64e0c34acc2d1
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17611
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/472707
Remove cross rank/cross channel dependency.
I guess this is a mistake that could lead to instabilities.
Tested on Lenovo T430 (Intel IvyBridge).
BUG=none
BRANCH=none
TEST=none
Change-Id: I9983d6c92b2729c602f4de1a593bd250e1fc80e4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c8cb97ea7
Original-Change-Id: I899db907cd2d2197fd81eda4c4656fb1e570c18f
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17610
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/472706
Calling disable_cache_as_ram() with valuables in stack is not
a stable solution, as per documentation AMD_DISABLE_STACK
should destroy stack in cache.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia9cd3c78925d7da22ba54ed9719df33867ca72e8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ba22e159bb
Original-Change-Id: I986bb7a88f53f7f7a0b05d4edcd5020f5dbeb4b7
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18626
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/471450
As we now apply asmlinkage attributes to romstage_main()
entry, also x86_64 passes parameters on the stack.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idc959f24a256aa5c77b00b030b2d01b0ea6dd127
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: df7ff31c59
Original-Change-Id: If9938dbbe9a164c9c1029431499b51ffccb459c1
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18624
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/471448
Add 100 Mhz reflock default values for Ivybridge.
Some values are extracted from MRC, those marked as
guessed needs to be verified.
Tested on Lenovo T430 (Intel IvyBridge) and DDR3-1800.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idf1d41e32a767fe7d250942834da69a2e2aecb1e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cb7d6a19bb
Original-Change-Id: Ife7f899b5fea02827ad998e9e8ab10ecaef61191
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17609
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/468732
Add support for 100MHz reference clock on ivybridge.
Allows to use more frequencies than sandybridge.
Tested on Lenovo T430 (Intel IvyBridge) on DDR3-1800.
BUG=none
BRANCH=none
TEST=none
Change-Id: I229d37937faff78ffa20a85e21f132d9008d26d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cab4d3df39
Original-Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17607
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/468730
Use Ivy Bridge specific magic values on Ivy Bridge instead
of Sandy Bridge values.
The values are extracted from MRC.bin.
Should increase raminit stability.
Tested on Lenovo T430 (Intel IvyBridge).
BUG=none
BRANCH=none
TEST=none
Change-Id: I900ed32dcb116d359c41e64fd096ffc814587926
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 77eaba3618
Original-Change-Id: I49fdfe5ae3e65704d22e083e8446e3f1069869bc
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17606
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/468729
Producer and consumer of these buffers now appear in same file.
Also add test for uninitialized NonVolatileStorage in SPI.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2af72fb451ee9faa5efa14fcbcaf8083a85f7b69
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 424c63950b
Original-Change-Id: Ibbf6581a0bf1d4bffda870fc055721627b538b92
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19037
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/467108
Only guard the parts that are problematic for romstage.
Also intention is to move AMD_S3LATE_RESTORE to ramstage in followup
work, it will need OemS3LateRestore.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idc337f6edd1d4647037fac177b8d0e85610e6596
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d5321c9c4
Original-Change-Id: Ie9c1fb3f3f0ab1951771ed829d4acdd8a59d8fbf
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19025
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/466060
Specification says to do CAR teardown as part of AmdInitPost().
Move initializing the final AGESA heap storage to AmdInitEnv()
so the buffer is not invalidated without writeback.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib17675c8cddb8b1266f389b6a2c505713897da64
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4a6e00fd36
Original-Change-Id: I3a5d497d0e25ec291f722e9f089bc8928238c3f9
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19024
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/466059
We define AGESA_LEGACY as an implementation of mainboard
that has its romstage main completely under mainboard/
directory. We have learnt from other platforms this approach
has several downsides when it comes to making platform-wide
improvements.
We start by creating per-family romstage.c file, which
boards will gradually take into use by removing the
AGESA_LEGACY Kconfig option we here apply to all of them.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3ff98b2ee71ee55883efe83372494d2181785388
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 967d94d626
Original-Change-Id: Id01931e185a023039a60af16a678de9966db8d65
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18619
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462938
This is a cosmetic change.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4536ce41bad5c02a10d008b52df66819b0910bd2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 50db9c99be
Original-Change-Id: Iea4dd97e9d83594447427abd9f844e507b805192
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18960
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/462935
Some Chrome OS boards previously didn't have a hardcoded vboot
configuration (e.g. STARTS_IN_BOOTBLOCK/_ROMSTAGE, SEPARATE_VERSTAGE,
etc.) selected from their SoC and mainboard Kconfig files, and instead
relied on the Chrome OS build system to pass in those options
separately. Since there is usually only one "best" vboot configuration
for a certain board and there is often board or SoC code specifically
written with that configuration in mind (e.g. memlayout), these options
should not be adjustable in menuconfig and instead always get selected
by board and SoC Makefiles (as opposed to some external build system).
(Removing MAINBOARD_HAS_CHROMEOS from Urara because vboot support for
Pistachio/MIPS was never finished. Trying to enable even post-romstage
vboot leads to weird compiler errors that I don't want to track down
now. Let's stop pretending this board has working Chrome OS support
because it never did.)
Change-Id: Ie50b79b1bb1acd10ed64332eaa763f0a6cb9ea17
Original-Change-Id: Ibddf413568630f2e5d6e286b9eca6378d7170104
Original-Reviewed-on: https://review.coreboot.org/19022
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id: 1210b41283
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/462007
Currently the `break` further down is called unconditionally as the
brackets for the body of the if statement are missing. Add those.
BUG=none
BRANCH=none
TEST=none
Change-Id: I738178ea9f4f92fad237cfec23acad6af17995dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b45bbb253f
Original-Change-Id: I34917a9877dcc882d880dedea689e1d72fe52888
Original-Found-by: Coverity (CID 1372941: Control flow issues (UNREACHABLE))
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18971
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/459504
Replace the use of the old device_t definition inside
northbridge/via/vx900.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iaf6a189371992a2f6d391802c1bb714d29baf8ba
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 823f7bb962
Original-Change-Id: I04292a6b698a42a5c582eddcef7cf5a235e1a464
Original-Signed-off-by: Antonello Dettori <dev@dettori.io>
Original-Reviewed-on: https://review.coreboot.org/17317
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/459659
It makes no sense to read SPDs if the system will reset anyway.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icc0587de64d04063c9203535a773ec1967604b23
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb5e77c478
Original-Change-Id: Id2ad9b04860b3e4939a149eef6b619a496179ff8
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17661
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/458348
This reuses some of gm45 code to set up the panel.
Panel start and stop delays and pwm frequency can now be set in
devicetree.
Linux does not make the difference between 945gm and gm45
for panel delays, so it is safe to assume the semantics of those
registers are the same.
The core display clock is computed according to "Mobile Intel 945
Express Chipset Family" Datasheet.
This selects Legacy backlight mode since most targets have some smm
code that rely on this.
This sets the same backlight frequency as vendor bios on Thinkpad X60
and T60.
A default of 180Hz is selected for the PWM frequency if it is not
defined in the devicetree, this might be annoying for displays that
are LED backlit, but is a safe value for CCFL backlit displays.
BUG=none
BRANCH=none
TEST=none
Change-Id: I86445ab53cb83bc5183fb998ca03e00b4746a33f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e079000dc
Original-Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18141
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/457362
Decode DDR2 SPD similar to DDR3 SPD decoder to ease
readability, reduce code complexity and reduce size of
maintainable code.
Rename dimm_is_registered to spd_dimm_is_registered_ddr3 to avoid
compilation errors.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2580a164627a0348da02aad6dbbe5311c442fe35
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6e53ae6f5c
Original-Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18273
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452895
