Use verb table values from AMI firmware, consolidate NID
definitions using azalia macros. Fixes headphone jack detection
and microphone.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7e80ecda87e9a8b406779c3d0f5a278ffc818636
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1e1bbb17a0
Original-Change-Id: Ia31be6efc7afe921ad91b400f66694d951f0a260
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19944
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/539229
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Initialize the audio codec without depending on DSP binary blobs.
The hda_verb.c was copied from the intel/kblrvp rvp7 variant, and the
hda_verb.h file was copied from the purism/librem13.
The IoBufferOwnership FSP option in devicetree has to be 0 for the azalia
driver to work.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2f67ea5ae06166c3f57057b8b0dc4e556c8817b1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: eacac20bd5
Original-Change-Id: Ifa36ac0839daedfa59c497057da0ace04d401f2a
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19943
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539228
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Some NVMe devices (Intel 600p series for example) seem to lock up
in D3 drive power state (L1.2 PCIe power state).
Disabling L1 substates fixes it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I664917f69ab2d60d72dd0896bd110e891f704a48
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d8cbd5633f
Original-Change-Id: I00a327dc91d443beb565fe4e72aaf816e40a007c
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19900
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/539227
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Enable libgfxinit.
Tested on Lenovo T430:
* LVDS
* VGA
* DP (using DP->HDMI adapter)
All three ports are working. The LVDS port is garbled under linux
when VGA or DP is connected, likely due to missing VBT.
BUG=none
BRANCH=none
TEST=none
Change-Id: I998a9b958a273de7331c9ac74a4e15b43be8b0b1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ea6f700632
Original-Change-Id: I665661e93724072d1e8412cfcc0e818f824c8cb0
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/20117
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/539225
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Use a GNVS variable to store the trackpad interrupt, in order to
support both SNB and IVB variants from a single build.
BUG=none
BRANCH=none
TEST=none
Change-Id: If873f366e1f760b843950225dfbd3cb1ab275cc7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d3b15c7821
Original-Change-Id: I53df35fff41f52a7d142aea9b1b590c65195bcfd
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20093
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539224
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Existing value was copied from librem13 v1 board, use value
obtained from AMI firmware.
TEST: Observe Windows boots correctly, function keys work
under both Windows and Linux.
BUG=none
BRANCH=none
TEST=none
Change-Id: I540b9124a88136993953026c845b8dc58b523682
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 739ded5c18
Original-Change-Id: I0ea6cc4602ce1047cb803acc65cbca1af1f480b0
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19945
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/539222
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
- remove unused I2C, serialIO defs
- set PL2 override, VR mailbox cmd based on SKL-U ref board,
as values copied from google/chell are for SKL-Y
BUG=none
BRANCH=none
TEST=none
Change-Id: I2efdc5fb22c2d67fde95f7de37478b9bb1e333e6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2ae2742065
Original-Change-Id: I3a138c28d0322df6cb41ec1a845ae31602cb69a7
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19941
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539219
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Update devicetree USB config based on board spec.
Leave OC pins set to skip since the info is unavailable.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9c6f4ea63dcd09ec9aed4e8ae4ee53d32dcfaf3f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2fa66164d8
Original-Change-Id: I2a4fe17ed7edacbbbaf56969f9d2801b45a20da9
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19940
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539218
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
TEST=Verified that board still boots to OS without any error.
Change-Id: I44c002e71e85017599a3f474941ced51c79e44d3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 296c79c9be
Original-Change-Id: I02d2a6cbcab92766a35993bfd20aaeed4ca22c90
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20143
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/539209
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Now that we dynamically disable TPM interface based on config options,
add support for generation of SPI TPM ACPI node if SPI TPM is used.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie64165f4b10fdae8ab64267f713a1feaaf1594c6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dec6d4e8c7
Original-Change-Id: I87d28a42b48ba916c70e45a061c5efd91a8a59bf
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20142
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539208
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Based on the config options selected, decide at runtime which TPM
interface should be disabled so that ACPI tables are not generated for
that interface.
TEST=Verified that unused interface does not show up in ACPI tables.
Change-Id: I62356b4f834c95f4d5a6982c9e2d1d2131d68092
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b2f423578e
Original-Change-Id: Iee8f49e484ed024c549f60c88d874c08873b75cb
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20141
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539207
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
There are many good reasons why we may want to run some sort of generic
callback before we're executing a reset. Unfortunateley, that is really
hard right now: code that wants to reset simply calls the hard_reset()
function (or one of its ill-differentiated cousins) which is directly
implemented by a myriad of different mainboards, northbridges, SoCs,
etc. More recent x86 SoCs have tried to solve the problem in their own
little corner of soc/intel/common, but it's really something that would
benefit all of coreboot.
This patch expands the concept onto all boards: hard_reset() and friends
get implemented in a generic location where they can run hooks before
calling the platform-specific implementation that is now called
do_hard_reset(). The existing Intel reset_prepare() gets generalized as
soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now
easily be added later if necessary). We will also use this central point
to ensure all platforms flush their cache before reset, which is
generally useful for all cases where we're trying to persist information
in RAM across reboots (like the new persistent CBMEM console does).
Also remove cpu_reset() completely since it's not used anywhere and
doesn't seem very useful compared to the others.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iaa2ba1292cb6dc1a4a8098ee256044691f42daba
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 01f9aa5e54
Original-Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19789
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539199
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Since this mainboard provides 3 COM ports on LPC, enable decoding of the
corresponding address range for COM 3.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iae09fc6a1ef0457322c9d5c84fefcd06832bf248
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a00d84536b
Original-Change-Id: I15c0748fce67eef46401c314f441aa45f5e3c5fa
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/20162
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/539196
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
- use Siemens NC FPGA driver for backlight brightness and PWM control
- set Dsave time for board reset after falling edge of signal xdsave
BUG=none
BRANCH=none
TEST=none
Change-Id: I6a51fce1d40d68dc2953a5f49213076f734121d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c21ba2cd3e
Original-Change-Id: I5077d4af162e54a3993e5e0d784a8356f51bd0c9
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/20161
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/539194
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The board dutifully registers an int15h handler and provides the
defaults to add a VGABIOS.
That should be good enough to initialize graphics through the VGABIOS
file.
Fixes build on Chrome OS configurations (at least until the Ada toolchain
situation is resolved over there).
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib535d95885606decf029206e615817a774e25029
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1d3661be0a
Original-Change-Id: I1d956b5a163b7cdf2bd467197fba95f16e5e8fa3
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://review.coreboot.org/20218
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/538580
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Too low gfx_uma_size can result in problems if the framebuffer
does not fit.
This partially reverts: 7afcfe0 "gm45: enable setting all vram sizes
from cmos"
BUG=none
BRANCH=none
TEST=none
Change-Id: I123e68c49e5329b5729cd593a0bb40f1156ec5f7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d65ff22988
Original-Change-Id: I485d24198cb784db5d2cfce0a8646e861a4a1695
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20194
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/538573
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The new config choice is called RUN_FSP_GOP. Some things had to happen
on the road:
* Drop confusing config GOP_SUPPORT,
* Add HAVE_FSP_GOP to chipsets that support it,
* Make running the GOP an option for FSP2.0 by returning 0
in random VBT getters.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icf0e46a75e0440c458f554de748d2e979dfffa30
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2e7f6ccafc
Original-Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19815
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/533093
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Provide all gfx init methods as a Kconfig `choice`. This elimates the
option to select native gfx init along with running a Video BIOS. It's
been only theoretically useful in one corner case: Hybrid graphics
where only one controller is supported by native gfx init. Though I
suppose in that case it's fair to assume that one would use SeaBIOS to
run the VBIOS.
For the case that we want the payload to initialize graphics or no
pre-boot graphics at all, the new symbol NO_GFX_INIT was added to the
choice. If multiple options are available, the default is chosen as
follows:
* NO_GFX_INIT, if we add a Video BIOS and the payload is SeaBIOS,
* VGA_ROM_RUN, if we add a Video BIOS and the payload is not SeaBIOS,
* NATIVE_VGA_INIT, if we don't add a Video BIOS.
As a side effect, libgfxinit is now an independent choice.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7d9ee12b47caa8909bd204929adecfc7f78f027c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d4ebeaf475
Original-Change-Id: I06bc65ecf3724f299f59888a97219fdbd3d2d08b
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19814
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/533052
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user
option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to
use the latter in a choice.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id68ef8d1fe1e00e03f8867d404c7b6b6e2ddd505
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 26ce9af9a0
Original-Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19813
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/533051
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers
that support a linear framebuffer. Some related settings moved to the
drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are
hardcoded.
BUG=none
BRANCH=none
TEST=none
Change-Id: If1746137edf2c976786e5b1a73c079d7e6c0f6d6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7971582ec4
Original-Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19800
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/533047
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER.
* Let drivers select it if they are in charge.
* Don't select it on the mainboard level if a driver handles it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I388e134017ee441cbd67b9a66fdbc07d992c9650
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ce642f08b9
Original-Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19791
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/533046
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Some renamings force us to update our code:
* Scan_Ports() moved into a new package Display_Probing.
* Ports Digital[123] are called HDMI[123] now (finally!).
* `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`.
Other noteworthy changes in libgfxinit:
* libgfxinit now knows about ports that share pins (e.g. HDMI1 and
DP1) and refuses to enable any of them if both are connected
(which is physically possible on certain ThinkPad docks).
* Major refactoring of the high-level GMA code.
BUG=none
BRANCH=none
TEST=none
Change-Id: I54b958e7fc141fdb112b0594b159e08d2981aef0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 989aae9f61
Original-Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/18770
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/533039
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
- remove old, buggy NGI code from falco/peppy variants
- remove superfluous INTEL_DP/INTEL_DDI configs, since already
selected by northbridge/haswell
- always use libgfxinit when use native init config selected
- enable NGI/libgfxinit for all slippy variants
The reset of the old Haswell NGI code will be cleaned up in
a subsequent patchset.
Test: select MAINBOARD_DO_NATIVE_VGA_INIT, observe panel init
using SeaBIOS and Tianocore payloads on peppy, wolf variants
[pg: add CQ-DEPEND to cover all pending graphics commits.
There are some fun little bugs and fixes along the chain.]
BUG=none
BRANCH=none
TEST=none
CQ-DEPEND=CL:538580
Change-Id: Ie127751e69309b2f3082e96ec1689c2600f4e526
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 472d5111ad
Original-Change-Id: Id5727cad7f714ffa57e77e2a25505e3c28f55237
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18824
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/533038
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
As the hardware designed on gru, the AP_I2C_TP_PU_EN (gpio3_b4) controlled
the SCL/SDA status to avoid leakage. And the gpio3_b4 of rk3399 pull
resistor is 26k~71k and 3.3v for supply power, and gpio3_b4 pin connected
2.2k resistor to i2c of TP device.
The default of this gpio status is pulled up during the start to bootup,
it's very weak drive for the TP device that maybe cause to trigger the
recovery process of elan's firmware.
Also, the Elan updated its firmware(102.0.5.0) to delay checking the
i2c of touchpad is greater than 1 second.
So we have to drive the stronger pull-up within 1 second of powering up
the touchpad to prevent its firmware from falling into recovery.
BUG=b:36705749
BRANCH=gru
TEST=none
Old-change-Id: I9a67d1c041afafde24ed9f00716ba41a9b41a8da
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ibb0ba3eff09de727e60a2bff5603deade4dc3d54
Reviewed-on: https://chromium-review.googlesource.com/537772
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: Ideb937d7f7bde4ac4203b3f9686cdedab43c446c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 049347fee0
Original-Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19678
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/531732
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Based on the Intel G41 chipset, ICH7 southbridge, and IT8720F Super I/O.
Tested, working:
* Booting Linux 4.11.3 and Windows 8.1 from USB and HDD
* Resume from S3 (Linux and Windows)
* Native raminit (DDR2-800)
* Native graphics init (SeaBIOS, Linux)
* Graphics init with VGA BIOS (SeaBIOS, Windows)
* PCI-E x16 PEG slot, PCI-E x1 slot from southbridge
* Realtek ALC888 HD Audio (including front panel and jack detection)
* Realtek R8168 Gigabit LAN
* Both SATA ports
* USB 1.1 and 2.0 devices (keyboard, mass storage)
* PC speaker beep
* COM header
* Super I/O Environment controller (temps, voltage, fans)
* PS/2 keyboard and mouse
* Flashing with `flashrom -p internal`
* 1MiB and 2MiB SPI flash chips
* CMOS gfx_uma_size
Appears, OS driver loads, but otherwise untested:
* IrDA header
* CIR header
* TPM header
Untested:
* S/PDIF digital audio
Tested, known broken:
* CMOS power_on_after_fail
* USB keyboard in secondary payloads
BUG=none
BRANCH=none
TEST=none
Change-Id: Iecb5ecf8a718755b5ce8f1ea52a803f609fea726
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 82651463e3
Original-Change-Id: Ifc4c8935b1a11e55f4bf6cfa484a8a8d09b1adda
Original-Signed-off-by: Samuel Holland <samuel@sholland.org>
Original-Reviewed-on: https://review.coreboot.org/20027
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531728
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
I updated my spike patch[1] to cleanly apply to current spike master.
As a side effect, the UART is now at 0x02100000.
[1]: https://github.com/riscv/riscv-isa-sim/pull/53
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibc0fdb395099e54c8aec2d37b28c2c4489500b08
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 035cf71822
Original-Change-Id: I4cb09014619e230011486fa57636abe183baa4be
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/20126
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/531726
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
For an unknown reason, the I2C ACPI devices were placed
under \SB intead of \SB.PCI0, as with all other non-Atom
based Intel platforms. While Linux is tolerant of this,
Windows is not. Correct by moving I2C ACPI devices where
they belong.
Also, adjust I2C devices at board level for google/rambi
as to not break compilation.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3afebbfaf56aa8cc9756d8878f9dda458d81f679
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e34a7705e6
Original-Change-Id: I4ef978214aa36078dc04ee1c73b3e2b4bb22f692
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20056
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531720
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The supported "G41C-GS" with a nuvoton nct6776 superio is actually
G41C-GS R2.0, which is different with the more easily-found revision
G41C-GS (R1.0) with Winbond W83627DHG superio, and should be ported
separately.
Photos for the two revision:
R1.0: https://web.archive.org/web/20160915160553/http://www.asrock.com/mb/photo/G41C-GS(L1).jpg
R2.0: https://web.archive.org/web/20160717203810/http://www.asrock.com/mb/photo/G41C-GS%20R2.0(L2).jpg
BUG=none
BRANCH=none
TEST=none
Change-Id: If8236eacdc35b3b22d813265e678f0321878bfee
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1517bab693
Original-Change-Id: If60a694bcf0652ab32c0ac75ceec7e27e11fe9eb
Original-Signed-off-by: Bill XIE <persmule@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19980
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/531710
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Update devicetree PCI config based on board spec:
- enable PCIe Root Ports 5 and 9 (wifi and nvme respectively)
- enable PCIe CLKREQ on RP9, disable on RP5
- enable USB OTG
- enable P2SB
Note: PCIe RP5 is on 0.1c.0 despite this being labeled as RP1
BUG=none
BRANCH=none
TEST=none
Change-Id: I8883f75cc65b56dc22e38ec5513149c0d9205137
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: debb785d59
Original-Change-Id: Ia71ed25bd41668df1ee3e4b4e28f54482722452c
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19939
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531693
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Needed for UEFI booting via Tianocore;
with PM timer disabled, payload hangs.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0ac172b90f496e44b117e3ec9a3809d7708b85b6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0ff3b73990
Original-Change-Id: I6c65cb9d3e6a10baea4cc1e2d9e94c36fe419561
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19938
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531692
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I34e5babc9b6f059d73d02348ad0fbcff07563527
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9d8cd507a6
Original-Change-Id: Ib63e5e8a1bcbc25c288dec7d1ef6c06239ada34b
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19937
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531691
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The FSP Temp RAM init will fail if the mircocode values are set
to 0. A valid microcode update needs to be included and its size
and offset need to be set in the config.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iac912e7350662a9e56aae6eb80b70fca5c032fd3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6b8570d864
Original-Change-Id: I26d05bd7b37c8d91bf34f399c7c4189f9d3dd34a
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19936
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531690
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Adding code to setup the spd information from sodimm.
Adapted from intel/kblrvp.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iffd47fc71def3533fb7545abe753fd09df77e184
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0e977fca9c
Original-Change-Id: I0403f999dac1bdef0e9e1abe7c9c62407e223bb1
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19935
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531689
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The GPIO configuration matches the one from the original BIOS.
Some configs don't make much sense, but I kept it as is so it
would match (such as a NC pin with TX set to 1, or RXINV enabled).
Remove unnecessary early GPIO config.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id7d3d5537260431af116b017ad5860d95adf781c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 34a30a648f
Original-Change-Id: Iaec8630cef9a523fb2e2503143aa4aa72fbedc1f
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19934
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531688
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Like other devices using ENE embedded controllers, the librem13v2
requires this config option for the PS2 keyboard and mouse
(trackpad) to function properly.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6a4309052ac05fafe88e7ec61e52dcdb5a320559
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2766ebf585
Original-Change-Id: Ifba13b93a1fe2e76b2790d1c273fd9e2b5368ab0
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19933
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531687
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add the initial directory for the port of the Librem 13 v2.
The base implementation was copied from the google/chell directory
and the chell references were replaced. spd directory was removed
since the RAM is not soldered on the MB. The Kconfig, board_info.txt
and devicetree.cb files were modified to match the Librem 13 v2
hardware information. The romstage.c, mainboard.c, Makefile.in and
dsdt.asl were modified to remove chromeos specific code. The boardid.c,
chromeos.c, chromeos.fmd, cmos.layout, ec.c, ec.h and smihandler.c
files were removed from the tree, and the acpi directory was replaced
with the acpi directory from the purism/librem13 board.
These changes allow us to remove the references to chromeos specific
code and allow coreboot to compile when the librem13v2 board is selected.
BUG=none
BRANCH=none
TEST=none
Change-Id: I44e7be967bf4e72e086aa26d332ac6dd16ae0608
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 047475cbd7
Original-Change-Id: I24263fde18fcea70163dbdc59df6ea1d98c97af8
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19932
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531686
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The FADT revision was set to 5, but we do not implement the
ACPI v5.0 specification, which prevents Windows from booting.
Setting it to v3 (matching most other boards) fixes the issue
and Windows now boots normally.
Bug found by Matt DeVillier, fix tested by Youness Alaoui on
Librem 13 v1 hardware.
Please also see commits 00d250e228 (intel/skylake: Switch FADT
to ACPI version 3.0) [1] and 27e6042bb7 (intel/apollolake:
Switch FADT to ACPI version 3.0) [2].
[1] https://review.coreboot.org/19453
[2] https://review.coreboot.org/19146
BUG=none
BRANCH=none
TEST=none
Change-Id: I24a5d1d75ef0fca5b273d8d32d20812089850812
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ab5b4c19c3
Original-Change-Id: Ide97cbf64f7b05018433436431ab4723b217fe22
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19985
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531685
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
A simple rename of the directory and the config values
and string in Kconfig/Kconfig.name/board_info.txt
It will be less confusing for users since the first models
are referred to as 'v1' everywhere now.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7a5bc84a564a6e75f0be9b34957ec09031fd368c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3c0d7d21ef
Original-Change-Id: I23fa977717230c2001868741bb684e9633a2c0bb
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19931
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/531201
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
For an unknown reason, the I2C ACPI devices were placed
under \SB intead of \SB.PCI0, as with all other non-Atom
based Intel platforms. While Linux is tolerant of this,
Windows is not. Correct by moving I2C ACPI devices where
they belong.
Also, adjust I2C devices at board level for intel/strago
and google/cyan as to not break compilation.
BUG=none
BRANCH=none
TEST=none
Change-Id: I39d845ba3b6d07d8bb5f63f663316750f03f20a6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6a67ffb6ea
Original-Change-Id: Iaf8211bd86d6261ee8c4d9c4262338f7fe19ef43
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20055
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531193
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibca733ea7c557899ff2f8d86362cccd7a41bbcca
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 397c7b3411
Original-Change-Id: Ie0b64eadc634049f6b65cf555407337fb7c4363c
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19976
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531192
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Switch from lapic to tsc.
Allows timestamps to be used in coreboot, as there's a reference
clock available to calculate correct time units.
Clean Kconfig, remove duplicated lapic code and include tsc dir for
LGA1155 boards.
Tested on Lenovo T430.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4c179884707380e1417a251db8f70d0a915572af
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b9959e279c
Original-Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/20044
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531190
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Update user facing camera i2c address to 0x36.
BUG=None
TEST=Build & boot on soraka. Make sure user facing camera is detected.
Change-Id: Id441041035e8a2962c859cac93d02858fc84d625
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5e10422df2
Original-Change-Id: I4645ae5734faef4b6a821c04ab817a7b99da6e4b
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20023
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/531188
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add support for ELAN 5515 device.
BUG=b:62331218
Change-Id: I1be493f7fbce0a31fefdc589c063d1561a384c5e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5677e7da4b
Original-Change-Id: Id91a41743330c9e356293cfda7b2e3743dcd480c
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20040
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528264
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
BUG=none
BRANCH=none
TEST=none
Change-Id: I280a7abeada01b4d158b2d65c3b59f1b98b81ad9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e18e6427d0
Original-Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/20029
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528259
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.
Run the command below to replace all occurences.
```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```
BUG=none
BRANCH=none
TEST=none
Change-Id: I881e55138a6114c67585ce37d4d719fe2626b83a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a8843dee58
Original-Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/20034
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528256
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Wrapping the long line tries to address a warning by `checkpatch.pl`,
but the line is still over 80 characters long.
BUG=none
BRANCH=none
TEST=none
Change-Id: If63c7ff3fb041b070dc815ffe05592edbb03dbec
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 619e83045a
Original-Change-Id: Ib75d4da1880624eb83f7a419cb6762f1c4c2a7b2
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/20033
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528255
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The comma-separated PCI vendor and device ID is used to associate the
VGA BIOS to the video device by using it as the file name of the VGA
Option ROM.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ideb80c381f491925dba2931448fe125a3f54e8f7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e213bf3767
Original-Change-Id: I755554eeb9a560d034d6e8fe49de619d800ea045
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18741
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528254
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Changes the offsets of some options so that options that span multiple
bytes are byte aligned.
To make the cmos.layout file more consistent some things where moved
around in the cmos.layout of thinkpads X200 and T400.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8736136043c526817fc12f52d37a5a1db4fb95b9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 00b9f4c4b1
Original-Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18321
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/528188
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
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