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UPSTREAM: purism/librem13v2: Enable SATA, disable eMMC support

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BUG=none
BRANCH=none
TEST=none

Change-Id: I34e5babc9b6f059d73d02348ad0fbcff07563527
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9d8cd507a6
Original-Change-Id: Ib63e5e8a1bcbc25c288dec7d1ef6c06239ada34b
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19937
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531691
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Youness Alaoui 2017-05-25 15:30:35 -05:00 • committed by chrome-bot
commit 8d87613cb4
1 changed files with 5 additions and 4 deletions
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9
src/mainboard/purism/librem13v2/devicetree.cb
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@ -28,10 +28,11 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "0"
register "EnableSata" = "1"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[2]" = "1"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
@ -40,8 +41,8 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "IshEnable" = "0"
register "PttSwitch" = "0"