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UPSTREAM: mainboard/google/{poppy,soraka}: Enable generation of SPI TPM ACPI node

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Now that we dynamically disable TPM interface based on config options,
add support for generation of SPI TPM ACPI node if SPI TPM is used.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ie64165f4b10fdae8ab64267f713a1feaaf1594c6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dec6d4e8c7
Original-Change-Id: I87d28a42b48ba916c70e45a061c5efd91a8a59bf
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20142
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539208
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Furquan Shaikh 2017-06-09 17:59:07 -07:00 • committed by chrome-bot
commit 7fde2e025d
3 changed files with 17 additions and 2 deletions
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1
src/mainboard/google/poppy/Kconfig
View file

@ -7,6 +7,7 @@ config BOARD_GOOGLE_BASEBOARD_POPPY
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_I2C_MAX98927
select DRIVERS_SPI_ACPI
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME

9
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View file

@ -428,7 +428,14 @@ chip soc/intel/skylake
device pci 1d.3 off end # PCI Express Port 12
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 on end # GSPI #0
device pci 1e.2 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
device spi 0 on end
end
end # GSPI #0
device pci 1e.3 on end # GSPI #1
device pci 1e.4 on end # eMMC
device pci 1e.5 off end # SDIO

9
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View file

@ -416,7 +416,14 @@ chip soc/intel/skylake
device pci 1d.3 off end # PCI Express Port 12
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 on end # GSPI #0
device pci 1e.2 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
device spi 0 on end
end
end # GSPI #0
device pci 1e.3 on end # GSPI #1
device pci 1e.4 on end # eMMC
device pci 1e.5 off end # SDIO