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UPSTREAM: nb/intel/gm45: Add romstage timestamps

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BUG=none
BRANCH=none
TEST=none

Change-Id: Ideb937d7f7bde4ac4203b3f9686cdedab43c446c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 049347fee0
Original-Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19678
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/531732
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Arthur Heymans 2017-05-12 11:54:08 +02:00 • committed by chrome-bot
commit 4abe65c4bd
4 changed files with 16 additions and 0 deletions
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4
src/mainboard/lenovo/t400/romstage.c
View file

@ -31,6 +31,7 @@
#include <console/console.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
#include <timestamp.h>
#include "dock.h"
#include "gpio.h"
@ -60,6 +61,9 @@ void mainboard_romstage_entry(unsigned long bist)
int cbmem_initted;
u16 reg16;
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
/* basic northbridge setup, including MMCONF BAR */
gm45_early_init();

4
src/mainboard/lenovo/x200/romstage.c
View file

@ -32,6 +32,7 @@
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
#include "gpio.h"
#include <timestamp.h>
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
#define MCH_DEV PCI_DEV(0, 0, 0)
@ -58,6 +59,9 @@ void mainboard_romstage_entry(unsigned long bist)
int cbmem_initted;
u16 reg16;
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
/* basic northbridge setup, including MMCONF BAR */
gm45_early_init();

4
src/mainboard/roda/rk9/romstage.c
View file

@ -32,6 +32,7 @@
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
#include <superio/smsc/lpc47n227/lpc47n227.h>
#include <timestamp.h>
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
#define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
@ -124,6 +125,9 @@ void mainboard_romstage_entry(unsigned long bist)
int cbmem_initted;
u16 reg16;
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
/* basic northbridge setup, including MMCONF BAR */
gm45_early_init();

4
src/northbridge/intel/gm45/raminit.c
View file

@ -25,6 +25,7 @@
#include <console/console.h>
#include <lib.h>
#include <delay.h>
#include <timestamp.h>
#include "gm45.h"
#include "chip.h"
@ -1713,6 +1714,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
int ch;
u8 reg8;
timestamp_add_now(TS_BEFORE_INITRAM);
/* Wait for some bit, maybe TXT clear. */
if (sysinfo->txt_enabled) {
@ -1825,4 +1827,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
raminit_thermal(sysinfo);
init_igd(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
}