Commit graph

354 commits

Author SHA1 Message Date
alokagar
e0b1a0dbec vc/intel/fsp/mtl: Update MTL fsp header files from 3471_91 to 4122_21
Update header files for FSP for Meteor Lake platform to version 4122_21,
previous version being 3471_91.

FSPS:
1. Added UPD's ThcMode, ThcWakeOnTouch
2. Reserved bit changes
FSPM:
1 Added PchHdaSubSystemIds

BUG=b:329548127
TEST=Able to build and boot google/rex to ChromeOS.

Change-Id: I4a1164060f7e91f8fa4ada60421bf87fb17ad541
Signed-off-by: alokagar <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84656
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-12-17 06:16:07 +00:00
Patrick Rudolph
4ce5304879 soc/intel/xeon_sp: Advertise DIMMs on skylake_sp as well
Add the MEMMAP_DIMM_DEVICE_INFO_STRUCT for skylake_sp and let common
code fill in the SMBIOS type 17 entries for all slots and found DIMMs.

This also allows to build dimm.c unconditionally on all xeon_sp socs.

Test: On ocp/tiogapass all DIMMs and slots are visible in SMBIOS.

Change-Id: I686b1e3ef946240785111f86a5f23a109a6a52ad
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-12-05 07:40:35 +00:00
Subrata Banik
c107755701 vc/intel/fsp: Update PTL FSP headers from 2382_01 to 2431.00
Update generated FSP headers for Panther Lake from 2431.00

Changes include:
- Update in FspmUpd.h : Adjusted offsets and updated comments.
- FspsUpd.h: added ThcInterruptPinMuxing, ThcMode and ThcWakeOnTouch
  UPDs
- MemInfoHob.h : Updated comments

BUG=b:378789201
TEST=Able to build google/fatcat

Change-Id: I1c1fed8f7ba9d25fdce5bbac3a9687800db33613
Signed-off-by: alokagar <alok.agarwal@intel.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-12-03 06:48:28 +00:00
Patrick Rudolph
3a7102d628 vendorcode/intel/fsp/skx_sp: Fix PCI domain scanning
Properly scan all logical stack when creating PCI domains.
Fixes PCI bus ranges being used on other stacks, since they look
unused, as not all stacks are checked.

Change-Id: I13c8b389a585dbccec182d3c98021f1d9d648b2c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-11-18 11:34:36 +00:00
Ronak Kanabar
4597fc331b vc/intel/fsp/raptorlake: Add FspProducerDataHeader.h header
This patch is to add FspProducerDataHeader.h header file to support MRC
version Info in RPL.

BUG=b:281846937
TEST=Able to build and boot google/brox.

Change-Id: Iaf7983fbe8f103d9f51065cd160177e2bde7fd3d
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-06 17:00:43 +00:00
Ronak Kanabar
4386948569 vendorcode/intel: Add edk2-stable202305 support
Add edk2-stable202305 support for MTL and RPL FSPs.
This patch includes (edk2/edk2-stable202302) all required
headers for edk2-stable202302 EDK2 tag from EDK2 github
project using below command:
    git clone -b edk2-stable202305 https://github.com/tianocore/edk2.git

commit hash: ba91d0292e593df8528b66f99c1b0b14fadc8e16

Only include necessary header files.

MdePkg/Include/Base.h was updated to avoid compilation errors
through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE.

Add following fixes from older Edk2
060492ecd2 Safe guard enum macro in SmBios.h
2bf9599cf1 Use fixed size struct elements
cf4c6fd225 Remove FSPM_ARCH_UPD config guard
dc781d3a83 Define FSP_SIG macro for FSP 2.x compatibility
d045074b91 Remove wchar_t asserts

Change-Id: I96f0d0e393d31b325f9e42e3494556a2f6e1228e
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-06 17:00:06 +00:00
Ronak Kanabar
7e5765710a vc/intel/fsp: Update PTL FSP headers from dummy headers to v2382_01
Update generated FSP headers for Panther Lake from v2382_01

Changes include:
- Update FspmUpd.h, FspsUpd.h, MemInfoHob.h and FirmwareVersionInfo.h

BUG=b:348678529
TEST=Able to build google/fatcat

Change-Id: Ibe382615db1a7c7a0841d8fe4ae43c226e2c2020
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-28 18:09:34 +00:00
Jincheng Li
87436bc4dd vc/intel/fsp/fsp2_0/graniterapids: Update to formal FSP header files
Change-Id: I6e94f44d50f2b53855adc1bb1cd6a1a5d9929003
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-09-26 15:08:50 +00:00
Jincheng Li
e626a4b0c0 vc/intel/fsp/fsp2_0/graniterapids: Update FSP headers
FSP n-1 headers in vc/intel/fsp/fsp2_0/graniterapid are updated to
pass compilation with full platform codes.

Change-Id: I1d13ddd4db8409a4928bd1bf152a9c284d138e48
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-09-13 11:09:57 +00:00
KunYi Chen
e9ed7928cf vc/intel/fsp: Update ADL N FSP headers from v5021.00 to v5132.00
Update generated FSP headers for ADL-N to MR5(5132_00)

Change-Id: I96fccbb92866fbc18c57187628612fda655cd7a7
Signed-off-by: KunYi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-08-26 11:02:44 +00:00
Jędrzej Ciupis
07dd73c921 soc/intel/jasperlake: Add CrashLog implementation for Intel JSL
Extend support for CrashLog to Intel Jasperlake based platforms.

This commit is based on 15cbc3b599,
originally reviewed on https://review.coreboot.org/c/coreboot/+/49943.

BUG=b:354834461
TEST=CrashLog can be enabled in Kconfig for Jasperlake based platforms
and can generate a BERT table, if enabled.

Change-Id: Ia18a79d8de849d556b4b8fd0e6b43090311eb23f
Signed-off-by: Jędrzej Ciupis <jciupis@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-08-22 13:13:47 +00:00
Saurabh Mishra
de8b77c384 vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile
Details:
- Skeleton files to compile google/fatcat mainboard.

BUG=b:348678529
TEST=Build verified on with using PTL SOC and google/fatcat mainboard.

Change-Id: I4c069ba64f487259ce746dc52296618d91209602
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83732
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2024-08-09 18:00:35 +00:00
Kulkarni, Srinivas
315dba7abb vc/intel/raptorlake: Update header files from 4435_00 to 5045_00
Update header files for FSP for Raptor Lake refresh platform to
version 5045_00, previous version being 4435_00.

FSPM:
1. Add IgdGsm2Size UPD
2. Comment added for Offset 0x0AB6

FSPS:
1. Add CepEnable UPD
2. Offset size updated for UPD ReservedCpuPostMemProduction
2. Comment added for Offset 0x104C

MemInfoHob:
1. Structure updated

BUG=b:355384183
Kit:https://www.intel.com/content/www/us/en/secure/design/confidential/
software-kits/kit-details.html?kitId=815173

Cq-Depend: chrome-internal:7554984
Change-Id: I80cccb6aaa8f3a97d860a1e7908bfac0435b1aec
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-09 15:51:27 +00:00
Chen, Yuchi
377b133359 vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC
Change-Id: I333b137c1dc08a3c06bdd3f7a78ca44a5dd043cc
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83192
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-08-06 16:46:50 +00:00
Varun Upadhyay
015c842620 vc/intel/fsp/twinlake: Update FSP headers to v5222.01
- Add Usb4CmMode & CnviWifiCore Upd support in FspsUpd.h
- Update UPD Offset in FspsUpd.h

BUG=b:354612775
TEST=Able to build and boot google/Tivviks

Change-Id: Ia68b6aa90c782a359b594f381e223772a897c6e6
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-27 03:41:54 +00:00
Ronak Kanabar
79be6da071 vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00
Update generated FSP headers for Alder Lake N from v5021.00

Changes include:
- Add FspProducerDataHeader.h header file
- Open Usb4CmMode & CnviWifiCore Upd in FspsUpd.h
- Update UPD Offset in FspsUpd.h

BUG=b:296433836
TEST=Able to build and boot google/nivviks

Change-Id: Ieb4cc8f2f83d8f6e821894f0ec2e56262a25743c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82780
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-04 13:59:30 +00:00
Ronak Kanabar
397a4965b2 Revert "vc/intel/fsp2/alderlake_n: Drop unused header files"
This reverts commit 79503ef515.

The Intel FSP repository at https://github.com/intel/FSP.git currently
lacks the Client ADL-N headers. The existing coreboot code references
the "IoT/AlderLakeN/" directory for these headers, but it is missing the
crucial FspProducerDataHeader.h file. Without this header, the ADL-N
platform is unable to utilize the appropriate MRC version needed for
updating MRC caches. This patch aims to restore the necessary FSP
headers for the ADL-N platform within the vendorcode directory.

Change-Id: I99e9d5a07b4ca8d1666e3fd50d3d363ed5d4618e
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-04 13:59:24 +00:00
Appukuttan V K
cf4c6fd225 vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard
This commit removes config guard around FSPM_ARCH_UPD from the
FspApi.h header file. This change is done to ensure
that this header file can be used with both x86_32 and x86_64
architectures and also with different FSP specification versions.

The following modifications are made:
- Removes PLATFORM_USES_FSP2_X86_32 config guard around
  FSPM_ARCH_UPD, this was added to isolate the structure from
  x64 build. This is not really required since the x64 build uses
  FSP2.4 structures.

BUG=b:343428206
TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex)

Change-Id: Idc849de73723036323f81dfd055730f6669cd52e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82425
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-31 10:46:13 +00:00
Appukuttan V K
e527e954be vc/intel/fsp/mtl: Add x86_64 FSP V3471.91 headers
This commit introduces new header files of V3471.91 for the x86_64
architecture in the fsp2_0/meteorlake directory. FSP2.4 brings FSP
64-bits support and the soc Kconfig file has been updated to select
this new header path when FSP2.4 is in use.

BUG=b:329034258
TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex)

Change-Id: Ib41b57e794311db729ac65a968f562aa127e86c3
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-05-30 13:22:10 +00:00
Appukuttan V K
acd0e1a5b8 vc/intel/fsp/mtl: Organize FSP headers into x86_32 directory
This commit moves FSP V3471.91 header files for Meteor Lake
into a new x86_32 directory to better organize the files based
on the architecture. The Kconfig file has been modified accordingly
to reflect the new paths of the relocated headers.

BUG=b:329034258
TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex)

Change-Id: Id30186a8b1b5a9082f498e18a3378f5e9907b668
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82424
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-30 13:21:58 +00:00
Subrata Banik
a6dfbeedff vc/intel/fsp: Refactor FSP header inclusion for EDK2 compatibility
This change refactors EDK2 essential header management within the FSP
directory to ensure compatibility.

Header selection is now dynamically based on:

* FSP specification version: Distinguishes between 1.1 and 2.x
* EDK2 revision (for FSP 2.x): Chooses the appropriate FSP info header

FSP Header
|
|-> FSP 1.1 specification FSP_INFO_HEADER
|-> FSP 2.0 specification EDK2 release
    |-> EDK2_2017 FSP_INFO_HEADER
    |-> EDK2_2020 FSP_INFO_HEADER
    |-> EDK2_2021 FSP_INFO_HEADER
    |-> EDK2_2023 FSP_INFO_HEADER

Any .C/.H file requires to include FSP_INFO_HEADER can now just add the
FSP header alone.

BUG=b:242829490
TEST=Able to build google/rex0 with 64-bit FSP.

Change-Id: I29e5002821843c9cffbc8f6317d1062175f014ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81623
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-04 06:29:20 +00:00
Subrata Banik
dc781d3a83 vc/intel/edk2: Define FSP_SIG macro for FSP 2.x compatibility
This patch introduces the FSP_SIG macro into EDK2 headers to ensure
compilation compatibility when using FSP 2.x specifications.

Previously, the macro was only defined for FSP 1.1.

BUG=b:242829490
TEST=Successful build of google/rex0 with 64-bit FSP.

Change-Id: I4f97fc303ca2881ccd17b4d149d01c3b671dbbde
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-04-04 06:28:38 +00:00
Jincheng Li
619535778c vc/intel/fsp/fsp2_0: Add GNR N-1 FSP headers
GNR N-1 FSP headers are a set of stub headers used to fulfill
build sanity check for GNR SoC and CRB codes before the formal
FSP headers are published. The N-1 headers are forward compatible
with the later formal headers.

Change-Id: I1c8125dd64e5a9619073c2f17aeade1d33607870
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-30 13:39:51 +00:00
Ronak Kanabar
14ea5c858a vc/intel/fsp/twinlake: Add FspProducerDataHeader.h header
This patch is to add FspProducerDataHeader.h header file to support MRC
version Info in TWL.

BUG=b:296433836

Change-Id: Ie33c681676d2a699b7aec8185dbdb90555ef8fe2
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81037
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-22 13:54:27 +00:00
Ronak Kanabar
760b572e0d vc/intel/edk2-stable202111: Resolve compilation error in EDK2 202111
Remove those MSVC compiler defaults checks so that the GCC defaults for
wchar_t can be used with UDK_202111_BINDING Kconfig.

Compilation error:
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h:807:25:
error: static assertion failed: "sizeof (L\'A\') does not meet UEFI
Specification Data Type requirements"
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h:807:25:
error: static assertion failed: "sizeof (L\"A\") does not meet UEFI
Specification Data Type requirements"

BUG=b:296433836
TEST=Able to build google/crassk with UDK_202111_BINDING.

Change-Id: Ib2716436a910b43a5e546afdedb9eec88c5da8c6
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81328
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22 13:38:46 +00:00
Arthur Heymans
d045074b91 vendorcode/edk2-stable202302: Remove wchar_t asserts
Remove those MSVC compiler defaults checks so that the GCC defaults for
wchar_t can be used. The FSP interface does not depend on wchar_t.

TEST: the resulting binaries are the same for intel/mtlrvp

Change-Id: I0ee1abc7e9ba46665838b63a6cfe0f4aa300114c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-03-14 15:53:09 +00:00
Ronak Kanabar
cee8eb25c8 vc/intel/fsp/mtl: Update header files from 3471_85 to 3471_91
Update header files for FSP for Meteor Lake platform to version 3471_91,
previous version being 3471_85.

FSPM:
1. Address offset changes

BUG=b:327688959
TEST=Able to build and boot google/rex to ChromeOS.

Change-Id: I5a71232018dfefec63b0a83d1e87717e238a4a0a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80782
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-08 07:15:22 +00:00
Shuo Liu
07cfe5392a soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SP
Move MEM_ADDR_64MB_SHIFT_BITS from FSP headers to Xeon-SP common layer
to reduce the dependency.

TEST=intel/archercity CRB

Change-Id: I4e1a652ad58233f7514cb9b23813d75144b8d435
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-05 21:40:56 +00:00
Ronak Kanabar
12756e6794 Revert "vc/intel/edk2: Remove edk2-stable202111 support"
This reverts commit b5f6320c69.

ADL-N FSP uses 202111 Edk2. There are structure definition changes
between 202005 and 202111. One of change is in FSP_INFO_HEADER structure.
This patch is to bring back support of edk2-stable202111.

BUG=b:296433836
TEST=Able to build google/crassk.

Change-Id: Id1d3e2c5b368a479e637f3ab3d18e242607849ed
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-05 14:06:34 +00:00
Kapil Porwal
6cc725466b vc/intel/fsp2/twinlake: Add FSP headers
Add FSP header files for Twin Lake. Currently these are just a copy of
ADL-N headers.

BUG=none
BRANCH=firmware-nissa-15217.B
TEST=Build and boot Google/Yaviks with Twin Lake kconfig enabled

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I37579335c784866ebbf978e28936abf046a85b48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-23 07:58:02 +00:00
Shuo Liu
3d5fd72c0f soc/intel/xeon_sp: Put SRAT util macros into Xeon-SP ACPI header
Macros MAX_ACPI_MEMORY_AFFINITY_COUNT and MAX_SRAT_MEM_ENTRIES_PER_IMC
are ACPI table specific, and could be used across Xeon-SP SoCs.
This patch moves their definition from FSP header to Xeon-SP layer
ACPI header.

TEST=intel/archercity CRB

Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: I6c3a84b04a452bc8d4217947a7d12f050c94b56b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80629
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-20 12:42:11 +00:00
Shuo Liu
3108ba5a07 soc/intel/xeon_sp: Use ACPI common flags in SRAT generation
Move the definition of SRAT memory flags (SRAT_ACPI_MEMORY_ENABLED
and SRAT_ACPI_MEMORY_NONVOLATILE) from FSP header to ACPI common
codes.

TEST=intel/archercity CRB

Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: I6aa5c20c9556fd5d680406518d19a83801b0852c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-02-20 12:40:48 +00:00
Martin Roth
4f1786dcac vendorcode: Rename Makefiles from .inc to .mk
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.

This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I80559b7c86a8fd2583cb0335279f676e0aa0209e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80067
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2024-01-24 08:34:46 +00:00
Kulkarni, Srinivas
8b89f89ecb vc/intel/fsp/mtl: Update header files from 3424_88 to 3471.85
Update header files for FSP for Meteor Lake platform to version 3471_85,
previous version being 3424_88.

FSPM:
1. Add 'DisplayGpioPinMux' UPDs
2. Address offset changes

BUG=b:318772151
TEST=Able to build and boot google/rex to ChromeOS.

Change-Id: I11c39fc2e3099d93a488e71d571ac1af02345fbd
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79829
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-07 05:35:33 +00:00
Subrata Banik
93902072e5 vc/intel/fsp/mtl: Add UPDs for Acoustic Noise Mitigation
Acoustic noise in PCBs is a common problem and be caused by a variety
of factors, including:

Mechanical vibrations, Electromagnetic interference (EMI) and/or Thermal
expansion.

This patch adds the UPDs to FSPM header file for mitigating the acoustic
noise.

FSPM:
1. AcousticNoiseMitigation
2. FastPkgCRampDisable
3. SlowSlewRate

BUG=b:312405633
TEST=Able to build and boot google/rex.

Change-Id: Iea0bfa2f92bb82e722ffc1a0b2f1e374b32e4ebc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79301
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
2023-12-20 04:25:06 +00:00
Kulkarni, Srinivas
520ca9a518 vc/intel/raptorlake: Update header files from 4301_01 to 4435_00
Update header files for FSP for Raptor Lake platform to version 4435_00,
previous version being 4301_01.

FSPM:
1. Options changed for Ppr Enable
2. Add 'Ppr Run Once' and 'Post Package Repair' UPD's

FSPS:
1. Add 'CpuPcieRpTestForceLtrOverride' UPD

MemInfoHob:
1. Structure updated

BUG=b:315234533
Kit: https://www.intel.com/content/www/us/en/secure/design/confidential/
software-kits/kit-details.html?kitId=793230

Cq-Depend: chrome-internal:6786881, chrome-internal:6787635
Cq-Depend: chrome-internal:6719974, chromium:5125983
Change-Id: I65b8a4b6c72f7ae3fff1ee6d073311d154cd6b69
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-17 20:14:45 +00:00
Kulkarni, Srinivas
7c6f1d570c vc/intel/raptorlake: Updating the FSP v4301.01 headers to Standard path
Move the existing FSP 4301.01 headers for Raptor Lake out of
subdirectory called 43101.01 to follow standard process.

Change-Id: I710f373acd37e9e0f8b50084a1a7e9fbda816e8c
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-14 03:23:31 +00:00
Kilari Raasi
b21bc9d9df vc/intel/fsp/mtl: Update header files from 3323_86 to 3424_88
Update header files for FSP for Meteor Lake platform to
version 3424_88, previous version being 3323_86.

FSPM:
1. Add `MarginLimitCheck` UPD
2. Add pre-memory graphics UPDs i.e `LidStatus`,
   `VgaInitControl`,`VbtPtr`,`VbtSize`,`VgaMessage`
3. Address offset changes

FSPS:
1. Add `Usb4CmMode` UPD
2. Address offset changes

BUG=b:310108425
TEST=Able to build and boot google/rex to ChromeOS.

Change-Id: I3f71cd739a607318fda06fa50d4a379d64857458
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78997
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-11 05:05:17 +00:00
Jeremy Compostella
e68650a656 vc/intel/fsp/mtl: Add Psi[1-3]Threshold UPDs to FSP-M header file
Export Power State Current 1, 2 and 3 Threshold configuration entries.

BUG=b:308002192

Change-Id: Iff4467720541efbdedace12431cd1f6f66fca8e6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-28 20:57:52 +00:00
Nick Vaccaro
55606625bb vc/intel/raptorlake: Use FSP v4301.01 headers for Google
Remove the existing FSP 4221.00 headers subdirectory called
4221.00_google, and have Google vendor devices use FSP 4301.01.

BUG=b:306181828
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel.

Change-Id: Ic64b3aec62f0d6302278393bf06d090f43c0d592
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-19 04:50:26 +00:00
Subrata Banik
17d619c25a vc/intel/fsp/mtl: Update header files from 3323.84 to MTL.3323.86
Update header files for FSP for Meteor Lake platform to version
3323.86, previous version being 3323.84.

FSPM:
1. Added new UPDs
    - AcLoadline
    - DcLoadline
    - LowerBasicMemTestSize
2. Address offset changes

BUG=b:301441204
TEST=Able to build and boot google/rex to ChromeOS.

Change-Id: I6c2f7f588874b37c52e3926c02e381ceff14f5af
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78065
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-09-23 09:25:50 +00:00
Sean Rhodes
e3d9b0aa3f vc/intel/raptorlake: Add the FSP v4301.01 headers
Move the existing FSP 4221.00 headers for Raptor Lake to a
subdirectory called 4221.00_google, and select this if the
vendor is Google.

Add the standard FSP 4301.01 headers to a separate directory,
from Intel download #686654, and select this for all other
vendors.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Icd99bdee1eeac70dfcaca3d07150d3de6bb83d81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77101
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-15 13:48:37 +00:00
Felix Singer
79503ef515 vc/intel/fsp2/alderlake_n: Drop unused header files
Change-Id: I870fa65ff05cf5907d62b3af1b2f9c4334b62603
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77260
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-08 02:46:01 +00:00
Subrata Banik
d0de6c2183 vc/intel/fsp/mtl: Update header files from 3292.83 to 3323.84
Update header files for FSP for Meteor Lake platform from 3292.83
to 3323.84.

The patch changess only a few spacing alignment for FSP-M header and
added few PPR (Post Package Repair) related variable for MemInfoHob
header.

BUG=b:297965979
TEST=Able to build and boot google/rex.

Change-Id: I65c6e05256a2ae9516449dbce62affd040cb0e56
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77561
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01 10:12:47 +00:00
Elyes Haouas
ce655f5bd5 vendorcode/intel/edk2: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: If093dc08c70c521cbef96ac5b5a7a46b37169bcd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-26 21:17:24 +00:00
Martin Roth
09202cce26 vc/intel: Remove unnecessary Kconfig options
These Kconfig options were being used basically as #define statements,
which is unnecessary. This isn't a good use of Kconfig options and would
be better just as #defines if actually needed.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If987b50d8ec3bb2ab99096e5e3c325e4d90a67a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-26 21:14:45 +00:00
Michał Żygowski
c651a27b53 vc/intel/fsp2_0: Add a copy of ADL-S IOT FSP MemInfoHob.h for RPL-S IOT
Similar situation happened last year when IoT FSP for ADL-S came out
before the Client FSP variant: https://github.com/intel/FSP/issues/83
It seems IoT FSP publishes the MemInfoHob.h file much later due to
legal reasons. Hack the missing file to get the builds using RPL-S IoT
FSP from repo working properly.

This change could be merged, subject for later revert (when the header
file is published).

Change-Id: Iec35db4573a3c3d011e4c1edf1c82a5c34438695
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-21 21:17:04 +00:00
Kilari Raasi
01f4f5db94 vc/intel/fsp/mtl: Add PsysPmax FspmUpd
This patch adds the PsysPmax Upd to FSPM header file.

FSPM:
1. Add 'PsysPmax' UPD
2. Address offset changes

BUG=b:295126631
TEST=Able to build and boot google/rex to ChromeOS.

Change-Id: I892b8c2d75e58a42d3f85006237827da01426ea7
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77244
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-21 09:34:07 +00:00
Dinesh Gehlot
b60cf3d135 vc/intel/fsp/mtl: Update header files from 3223.80 to 3292.83
Update header files for FSP for Meteor Lake platform to version 3292.83,
previous version being 3223.80.
The patch doesn't include any function changes, only a few comments and
headers have been changed.

BUG=b:295126631
TEST=Able to build and boot google/rex to ChromeOS.

Change-Id: I27f88732bfafd4732ea39bf9c54e18341dd26cf9
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-18 14:12:41 +00:00
Sean Rhodes
9a04ec6c9f vendorcode/fsp: Rename GLK to Gemini Lake to match other SOCs
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic559b78e6444acec36d437fe3c139b692a3f4d0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77126
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-08-16 15:20:52 +00:00