soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SP

Move MEM_ADDR_64MB_SHIFT_BITS from FSP headers to Xeon-SP common layer
to reduce the dependency.

TEST=intel/archercity CRB

Change-Id: I4e1a652ad58233f7514cb9b23813d75144b8d435
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

src/soc/intel/xeon_sp/include/soc/util.h

@@ -6,6 +6,8 @@
 #include <cpu/x86/msr.h>
 #include <hob_iiouds.h>
 
+#define MEM_ADDR_64MB_SHIFT_BITS 26
+
 void lock_pam0123(void);
 void unlock_pam_regions(void);
 

src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h

@@ -57,7 +57,6 @@ are permitted provided that the following conditions are met:
 #define MAX_IMC_PER_SOCKET                2
 
 #define MEM_TYPE_RESERVED (1 << 8)
-#define MEM_ADDR_64MB_SHIFT_BITS 26
 
 #define NGN_MAX_SERIALNUMBER_STRLEN 4
 #define NGN_MAX_PARTNUMBER_STRLEN 20

src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h

@@ -46,7 +46,6 @@ are permitted provided that the following conditions are met:
 #define MEMTYPE_VOLATILE_MASK  (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK)
 
 #define MEM_TYPE_RESERVED (1 << 8)
-#define MEM_ADDR_64MB_SHIFT_BITS 26
 
 //------------------------------------------------------------------------------------
 // Uncomment line(s) below to override macro definitions in FSP MemoryMapDataHob.h

src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h

@@ -43,7 +43,6 @@ are permitted provided that the following conditions are met:
 #define MAX_IMC_PER_SOCKET                2
 
 #define MEM_TYPE_RESERVED (1 << 8)
-#define MEM_ADDR_64MB_SHIFT_BITS 26
 
 //
 //  System Memory Map HOB information